Annex A (informative) SCSI signal sequence example

This annex is included to provide an example of the signal sequencing of an I/O process that includes most of the SCSI bus phases (see figure A.1). In this example, the target does not disconnect from the SCSI bus prior to completing the I/O process.

In a typical system, the computer's host adapter acts as the initiator and the peripheral device's controller acts as the target. In general, this International Standard does not attempt to distinguish between a computer and its host adapter. These functions may be separate or merged. The term initiator encompasses both. The term target refers to the controller portion of the peripheral device, which may be separate (bridge controller) from the peripheral device or merged with it (embedded controller). The term SCSI device refers to a device that may be connected to the SCSI bus. An SCSI device may act in the initiator role, the target role, or both roles.

The following notes apply to figure A.1.

DATA BUS NOTES

1) DB(7) is the most significant bit.
2) DB(7) is the highest priority arbitration bit.
3) DB(P) is the data parity bit (odd). Parity is not valid during the ARBITRATION phase.

BUS PHASE NOTES

1) BUS FREE phase. BUS FREE phase begins when the SEL and BSY signals are both continuously false for a bus settle delay. It ends when the BSY signal becomes true. (In the SCSI-1 single- initiator option, BUS FREE phase could also end when the SEL signal became true.)
2) ARBITRATION phase. This phase is documented as mandatory in SCSI-2. In SCSI-1, this phase was optional.

At least one bus free delay after first detecting BUS FREE phase, but no more than a bus set delay after the bus was last free, the initiator asserts the BSY signal and its assigned SCSI device ID bit on the DATA BUS. The initiator waits an arbitration delay, then examines the DATA BUS. If a higher priority SCSI device ID bit is true, the initiator loses arbitration and may release the BSY signal and its SCSI ID bit. Otherwise, the initiator wins arbitration and asserts the SEL signal. All SCSI devices must release the BSY signal and their SCSI ID bit within a bus clear delay after the SEL signal becomes true (even if they have not yet examined the DATA BUS). The winning SCSI device waits at least a bus clear delay plus a bus settle delay after asserting the SEL signal before changing any signals on the bus.

3) SELECTION phase. The I/O signal is false during this phase to distinguish it from the RESELECTION phase.

NON-ARBITRATING SYSTEMS (only permitted in SCSI-1): In such systems, the initiator waits at least a bus clear delay after detecting BUS FREE phase, then it asserts the target's SCSI ID bit and, optionally, the initiator's SCSI ID bit on the DATA BUS. After at least two deskew delays, the initiator asserts the SEL signal.

ARBITRATING SYSTEMS: In such systems, the SCSI device that won arbitration has both the BSY and SEL signals asserted. After at least a bus clear delay plus a bus settle delay, it places both the target's and the initiator's SCSI ID bits on the DATA BUS. At least two deskew delays later, it releases the BSY signal.

ALL SYSTEMS: The target determines that it is selected when the SEL signal and its SCSI ID bit are true and the BSY and I/O signals are false for at least a bus settle delay. The target then asserts the BSY signal within a selection abort time after it last determined that it was still being selected. (The target is not required to respond to a selection within a selection abort time; but it must ensure that it will not assert the BSY signal more than a selection abort time after the initiator aborts a selection attempt.)

At least two deskew delays after the initiator detects the BSY signal is true, it releases the SEL signal.

4) MESSAGE OUT phase. During this phase the initiator sends an IDENTIFY message to the target. The target asserts the C/D and MSG signals and negates the I/O signal for the message transfer. After detecting the assertion of the REQ signal, the initiator negates the ATN signal before asserting the ACK signal. (Refer to the handshake procedure for the command phase.)
5) COMMAND phase. The target asserts the C/D signal and negates the I/O and MSG signals for all of the bytes transferred during this phase. The direction of transfer is from the initiator to the target.

HANDSHAKE PROCEDURE: The target asserts the REQ signal. Upon detecting the REQ signal is true, the initiator drives the DATA BUS to the desired value, waits at least one deskew delay plus a cable skew delay and then asserts the ACK signal. The initiator continues to drive the DATA BUS until the REQ signal is false.

When the ACK signal is true at the target, the target reads the DATA BUS and then negates the REQ signal.

When the REQ signal becomes false at the initiator, the initiator may change or release the DATA BUS and negate the ACK signal.

The target may continue to request command bytes by asserting the REQ signal again. The number of command bytes is determined by the group code (most significant 3 bits) that is contained in the first command byte.

6) DATA IN phase. The target asserts the I/O signal and negates the C/D and MSG signal for all of the bytes transferred during this phase. The direction of transfer is from the target to the initiator.

HANDSHAKE PROCEDURE: The target first drives the DATA BUS to their desired values, waits at least one deskew delay plus a cable skew delay, and then asserts the REQ signal. The target continues to drive the DATA BUS until the ACK signal is true.

When the REQ signal is true at the initiator, the initiator reads the DATA BUS and then asserts the ACK signal.

When the ACK signal is true at the target, the target may change or release the DATA BUS and negate the REQ signal.

When the REQ signal is false at the initiator, the initiator negates the ACK signal. After the ACK signal is false, the target may continue the transfer by driving the DATA BUS and asserting the REQ signal as described above.

7) DATA OUT phase (not shown in the figure). The target negates the C/D, I/O, and MSG signals for all of the bytes transferred during this phase. The direction of transfer is from the initiator to the target. (Refer to the handshake procedure for the command phase.)
8) STATUS phase. The target asserts the C/D and I/O signals and negates the MSG signal for the byte transferred during this phase. The direction of transfer is from the target to the initiator. (Refer to the handshake procedure for the DATA IN phase.)
9) MESSAGE IN phase. The target asserts the C/D, I/O, and MSG signals during the byte transferred during this phase. Typically, a command COMPLETE message would be sent at this point. The direction of transfer is from the target to the initiator. (Refer to the handshake procedure for the DATA IN phase.)
10) BUS FREE phase. The target returns to BUS FREE phase by releasing the BSY signal. Both the target and the initiator release all bus signals within a bus clear delay after the BSY signal is continuously false for a bus settle delay.

Figure A.1 - SCSI signal sequence example