Observations:

1) noise level dependent on FPGA internal operation(shift register) ~ x2

2) measuring at sink (test board)

grounded at source to TB GND à 50 / 150 mV

grounded at source to daughter GND à 80/180 mV

normal operation (grounded on FPGA) à 200 /650 mV

3) measuring at source

test channel (disconnected) 80 mV

normal channel ~150 mV (1/2 sink voltage)