-------------------------------------------------------------------------------- Release 7.1.02i Trace H.40 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. C:/ISE71/Xilinx/bin/nt/trce.exe -ise d:\newjem\cpmtest\cpmtest.ise -intstyle ise -e 3 -l 3 -s 8 -xml top top.ncd -o top.twr top.pcf Design file: top.ncd Physical constraint file: top.pcf Device,speed: xcv1000e,-8 (PRODUCTION 1.69 2005-01-22) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. ================================================================================ Timing constraint: NET "inp_IBUF" MAXDELAY = 2 ns; 1 item analyzed, 0 timing errors detected. Maximum net delay is 1.273ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "ing" MAXSKEW = 0.15 ns; 1 item analyzed, 0 timing errors detected. Maximum net skew is 0.149ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clocka = PERIOD TIMEGRP "clocka" 25 ns HIGH 50%; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clockb = PERIOD TIMEGRP "clockb" TS_clocka PHASE 1.56 ns HIGH 50%; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cka2 = PERIOD TIMEGRP "cka2" TS_clocka / 2 HIGH 50%; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_ckb2 = PERIOD TIMEGRP "ckb2" TS_clockb / 2 HIGH 50%; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cka4 = PERIOD TIMEGRP "cka4" TS_cka2 / 2 HIGH 50%; 12 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 5.060ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_ckb4 = PERIOD TIMEGRP "ckb4" TS_ckb2 / 2 HIGH 50%; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock clocka ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clocka | 3.126| 2.530| | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 12 paths, 2 nets, and 41 connections Design statistics: Minimum period: 5.060ns (Maximum frequency: 197.628MHz) Maximum net delay: 1.273ns Maximum net skew: 0.149ns Analysis completed Wed Jun 08 10:16:00 2005 -------------------------------------------------------------------------------- Peak Memory Usage: 98 MB