http://www.staff.uni-mainz.de/uschaefe/browsable/L1Calo/TopoTests/

Test plan and decisions to be taken ……………. 11/10/2013 16:20:48

To check:

Can temperatures be read out of MiniPODs?

How about Voltages on MiniPOD and FPGA?

Open decisions for production module:

Configurator scheme?

USB/JTAG daughter?

User I2C monitor path distinct from IPMB?

I2C fan-out scheme: direct from FPGA / fan-out chip?

Test plan:

B/Scan: Are we convinced now that initial boundary scan test results match reality?

Remark: In case we use 1.8V->2.5V LVDS anywhere on the design, that will work properly after FPGA configuration, but might fail boundary scan!!! Risk of destruction!

Real-time path:

All inputs and outputs with IBERT at 10, 6.4G (done?)

Do we require any optimization of MGT/ MiniPOD parameters?????

All optical input and output paths at 6.4G and 10G, ramp test

- Test with loopback, data driven from GCK!

o same refclk Xtal

o TTCclock on transmission and reception

o TTCclock on transmission, xtal on reception

Test the firmware to the extent possible:

- Input alignment 32-bit

- Input alignment 128 bit

- Playback, spy

- ROD interface

- Any idea how to test algorithms? M

Electrical out: build electrical adapter!

TTCdec

- Clocks

- L1a

- Bcreset

- Bcast

- I2c control

- How about module ID setting?

Configuration:

- CF card! and JTAG

- To get rid of Xilinx box, test JTGA adapters!

IPMC: Require conversion to crate operation w. ATC250

- Switch on and off

- Defer environment monitoring tests?