Some rules for VHDL coding and implementation:

· When starting a project, use the most recent design tools only

· Try to keep up with new design tools

· If required to freeze the

· For reason of compatibility, do not assume the use of graphical tools for representation of code, make sure your VHDL plain text is humanly digestible

o Do not excessively partition your code in separate entities and separate files

o Do not use large numbers of processes. A single process per clock should do (see also latency), with a maximum of two conditional sections dependent on the clock

§ If rising_edge …,  If falling_edge …

§ Do not use clock’event

· Use automatically generated code where appropriate

o Do not modify the generated code, since it might have to be regenerated for new design software versions

· Use fully synchronous code only

o Identify clocks, make sure they

o Capture all input signals on flip-flops

o Register all output signals on flip-flops

o No asynchronous paths

o No latches

o Minimize number of clocks

§ Use clock enables rather than divided clocks

§ If necessary, derive secondary clocks with help of clock managers only

o Cross clock domains with help of well documented IP only, do not write your own synchronizers

· Use processes dependent on a single clock only

· Use timing constraints on all clocks

· Follow the L1Calo coding rules

· Signals, variables, comments in (meaningful) English language only

· For any code violating above rules, consult your colleagues!

Finally: read and understand all warnings generated by your synthesis and implementation tools !