Generated from <b>fFEX_Block_MGTCLOCK_BB.sch</b><p> by exp-lbrs.ulp Date: >LAST_DATE_TIME Sheet: >SHEET REV: TITLE: Document Number: >DRAWING_NAME BB R Clock Multiplexer SEL1 SY58028UMG SEL0 INPUT SY58034UMG IN0 IN1 SEL Fanout_CML_DC SY58034UMG IN0 IN1 SEL Fanout_CML_AC SY89838U IN0 IN1 SEL Fanout_LVDS_AC Jitter Cleaner SI5345A-D-GM INPUT I2C HEADER Serial ID D1 D2 D4 D3 OE* S1A S2A S3A S4A S1B S2B S3B S4B SE TMUX1574 VCC VIN VOUT1 VOUT2 PGOOD1 PGOOD2 PMBUS RUN1 RUN1 >value LEVEL TRANSLATOR SN74AVC4T774 A1 A2 A3 A4 B1 B2 B3 B4 VA VB ADM1260 VX1 VX3 VX2 VX4 VP1 VP2 VP3 VP4 VX5 PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 PDO7 PDO8 PDO9 PDO10 VH SCL/SDA CCL/CDA 12W FireFly_TX 3V3 3V8 VIN RUN1 RUN2 PMBUS VOUT1 VOUT2 PG1 LTM4681 VOUT3 VOUT4 PG2 PG3 PG4 RUN3 RUN4 <b>FRAME</b><p> DIN A3, landscape with extra doc field Generated from <b>BB_Stefan_Topo_draft.sch</b><p> by exp-lbrs.ulp MGTREFCLK0_120 MGTREFCLK0_121 MGTREFCLK0_122 MGTREFCLK0_123 MGTREFCLK0_124 MGTREFCLK0_125 MGTREFCLK0_126 MGTREFCLK0_127 MGTREFCLK0_128 MGTREFCLK0_129 MGTREFCLK0_130 MGTREFCLK0_131 MGTREFCLK0_132 MGTREFCLK0_133 MGTREFCLK1_120 MGTREFCLK1_121 MGTREFCLK1_122 MGTREFCLK1_123 MGTREFCLK1_124 MGTREFCLK1_125 MGTREFCLK1_126 MGTREFCLK1_127 MGTREFCLK1_128 MGTREFCLK1_129 MGTREFCLK1_130 MGTREFCLK1_131 MGTREFCLK1_132 MGTREFCLK1_133 MGTREFCLK0_220 MGTREFCLK0_221 MGTREFCLK0_222 MGTREFCLK0_223 MGTREFCLK0_224 MGTREFCLK0_225 MGTREFCLK0_226 MGTREFCLK0_227 MGTREFCLK0_228 MGTREFCLK0_229 MGTREFCLK0_230 MGTREFCLK0_231 MGTREFCLK0_232 MGTREFCLK0_233 MGTREFCLK1_220 MGTREFCLK1_221 MGTREFCLK1_222 MGTREFCLK1_223 MGTREFCLK1_224 MGTREFCLK1_225 MGTREFCLK1_226 MGTREFCLK1_227 MGTREFCLK1_228 MGTREFCLK1_229 MGTREFCLK1_230 MGTREFCLK1_231 MGTREFCLK1_232 MGTREFCLK1_233 XCVU13PFGLA2577 MGTREFCLK0_134 MGTREFCLK0_135 MGTREFCLK0_234 MGTREFCLK0_235 MGTREFCLK1_134 MGTREFCLK1_135 MGTREFCLK1_234 MGTREFCLK1_235 SLR 1 SLR 2 SLR 3 SLR 4 SLR 1 SLR 2 SLR 3 SLR 4 >value CLOCK Date: >LAST_DATE_TIME Sheet: >SHEET REV: TITLE: Document Number: >DRAWING_NAME MGTRX_120 XCVU13PFGLA2577 SLR 1 SLR 2 SLR 3 SLR 4 SLR 1 SLR 2 SLR 3 SLR 4 MGTRX_121 MGTRX_122 MGTRX_123 MGTRX_124 MGTRX_125 MGTRX_126 MGTRX_127 MGTRX_128 MGTRX_129 MGTRX_130 MGTRX_131 MGTRX_132 MGTRX_133 MGTRX_134 MGTRX_135 MGTTX_120 MGTTX_121 MGTTX_122 MGTTX_123 MGTTX_124 MGTTX_125 MGTTX_126 MGTTX_127 MGTTX_128 MGTTX_129 MGTTX_130 MGTTX_131 MGTTX_132 MGTTX_133 MGTTX_134 MGTTX_135 MGTRX_220 MGTRX_221 MGTRX_222 MGTRX_223 MGTRX_225 MGTRX_224 MGTRX_226 MGTRX_227 MGTRX_228 MGTRX_230 MGTRX_229 MGTRX_231 MGTRX_232 MGTRX_233 MGTRX_235 MGTRX_234 MGTTX_220 MGTTX_221 MGTTX_222 MGTTX_223 MGTTX_224 MGTTX_225 MGTTX_226 MGTTX_227 MGTTX_228 MGTTX_229 MGTTX_230 MGTTX_231 MGTTX_232 MGTTX_233 MGTTX_234 MGTTX_235 12W FireFly_RX 12W FireFly_TX <b>FRAME</b><p> DIN A3, landscape with extra doc field Generated from <b>Clocking_and_links_only_V2_BB.sch</b><p> by exp-lbrs.ulp MEZZANINE FPGA_A PIM400 VXx = 0.573V - 1.375V 12V/600W ATCA -48V_AF -48V_BF -48V_ARTN -48V_BRTN -48V_OUT -48V_RTN +3,3V_UP -48V_IN -48V_RTN ON/OFF +12V_OUT IPMC I2C +3,3V_UP Mgt_I2C VIN VOUT1 VOUT2 LTM4700 PGOOD RUN1 RUN2 PMBUS VIN VOUT1 VOUT2 LTM4681 PGOOD RUN1 RUN2 PMBUS VOUT3 VOUT4 Dual 50A or Single 100A VIN: 4.5V to 16V VOUT: 0.6V to 1.8V QUAD 31.25A or Single 125A VOUT: 0.5V to 3.3V VIN: 4.5V to 16V 12V_ENABLE ZONE 1 POWER SUPPLY MAINBOARD FOR DEBUG MEZZANINE_BOARDLEVEL VCCINT_U1 0.7V 3V3_BL 2V5_BL 1V8_BL HEADER FOR DEBUG 2x6A J5 HA[0..7] I2C_A I2C_B HA[0..7] I2C_IPMBA I2C_IPMBB 3V3_UP VCCO2_UltraZED UtraZED 2x50A =1 XOR ADM_QBV_12V_EN + LTM4681 3V3_BL 2V5_BL 3V8_FIREFLY_BIAS IPMC[0..7] HA[0..7] IPMC[0..7] Dual 6A or Single 12A VIN: 2.9V to 20V VOUT: 0.4V to 5.5V CPLD1 1V8_U1 VCCAUX_U1 MGTVCCAUX_U1 VCCINT_U1 MGTYAVCC_U1 MGTYAVTT_U1 3V8_FIREFLY_BIAS 1V8_JC EN_VCCINT_U1 EN_VCCINT_GT_U1 EN_GTSVCC_U1 EN_GTAVTT_U1 EN_3V3_BL EN_2V5_BL EN_1V8_BL EN_VCCAUX_U1 EN_3V8_FF EN_1V8_JC ADM_QBV_12V_EN 1 2 3 5 6 7 8 9 10 13 14 12V_EN_SPARE I:/fFEX_Document/Design/UltraZED/UZ_PWR_requires.bmp I:/fFEX_Document/Design/UltraZED/UZ_PWR_requires.bmp SMBUS InterChipBus 2 2 0.7V 0.9V 1.2V VPx = 0.573 - 1.375V 1.250 - 3.000V 2.500 - 6.000V VH = 2.50 - 6.00V = 6.00-14.40V MEZZ_JX2 C23 CTRL 3V3_BL Leveltranslate EN_VCCINT_U1 EN_MGTAVCC_U1 EN_MGTAVTT_U1 EN_MGTAVCC_U2 EN_MGTAVTT_U2 EN_3V3_BL EN_2V5_BL EN_1V8_BL EN_3V8_FF EN_1V8_JC +12V_IN +3,3V_UP A B PROG_CPLD BMR4582211002 LTM4681 VCCINT_GT_U1 0.8V GTAVCC_U1 0.92V GTAVTT_U1 1.2V VCCAUX_U1 1.5V 1V8_BL EN_VCCINT_GT_U1 EN_GTSVCC_U1 EN_GTAVTT_U1 EN_VCCAUX_U1 VCCINT_GT_U1 0.8V GTSVCC_U1 0.92V GTAVTT_U1 1.2V VCCAUX_U1 1.5V REFCLK1 REFCLK0 GTR [0..3] MIO 501 [26..51] GTR0 UltraZed EV IPbus U1<0..3>(RX+TX) IPbus U2<0..3>(RX+TX) ETH_MD 4 diff+2 MIO(44..51) MIO(32..35) PS_ETH_MD_P/N[0..3] MGTRAVCC_0.85V/2A 1V8_BL 1V8_U1 3V3_BL MGTRAVTT_1.8V/2A MGTAVCC_0.9V/3A MGTAVTT_1,2V/3A 12V_BL IPMC +3,3V_UP I2C 12V_ENABLE HA[0..7] I2C_IPMBA I2C_IPMBB USER IO[0..8] 3V3_UP 3V3_BL MIO(42,43) 3V3_UP to PIM400 PHY_PS_ETH_MD1P/N PHY_PS_ETH_MD2P/N PHY_PS_ETH_MD3P/N PHY_PS_ETH_MD4P/N PHY_ETH_LED0/1 8diff 2diff 1V8_BL TS621E BAS40-04 VCC_BATT RJ45 RJ45 GB_A/B/C/D zynq(PS) 4 diff 2 diff /SGMII) 2 diff /SGMII) ATCA ZONE 1 J5 HA[0..7] I2C_A I2C_B IPMC MGT RX/TX MGT RX/TX IPBUS U1 GTH [0..3] GTH [4..7] REFCLK2 REFCLK3 REFCLK4 REFCLK5 GTH [8..11] GTH [12..15] REFCLK6 GTH<8..11> GTH<4..7> GTH<0..3> FireFly 4RX + 4TX FELIX GTH<12..15> 8diff IPBUS U2 QUAD 225 QUAD 226 QUAD 227 QUAD 224 REFCLK0 REFCLK1 REFCLK2 REFCLK3 GTR1 GTR2 GTR3 2diff 2diff CPLD1 CTRL_MEZZ IPBUS PHY CTRL_MEZZ_DCS PHY CTRL_MEZZ SSD m.2 CTRL_MEZZ MAC PHY CTRL_MEZZ SPARE 8diff CTRL_MEZZ DUAL UART CTRL_MEZZ MicroSD CTRL_MEZZ SSD m.2 CTRL MIO(37..40) 2diff CTRL_MEZZ SPARE 4 ULTRAZED_MGT3_IN 320.64 MHz 5 ULTRAZED_MGT1_IN 156.25 MHz 9 ULTRAZED_JC_FIXED_CLK2_IN 88 MHz 3 ULTRAZED_MGT2_IN 240.48 MHz 7 ULTRAZED_MGT1_IN 156.25 MHz 6 ULTRAZED_JC_FIXED_CLK1_IN 88 MHz 8 ULTRAZED_MGT4_IN 80.16 MHz 10 ULTRAZED_JC_FIXED_CLK4_IN 11 ULTRAZED_JC_FIXED_CLK5_IN QUAD 224 REFCLK7 QUAD 225 QUAD 226 QUAD 227 CTRL_MEZZ_SPARE CLK1 CTRL_MEZZ_SPARE CLK2 CTRL_MEZZ_SPARE CLK3 QUAD 227 HP_DP[0..23]_BANK64 HP_DP[24..47]_BANK65 HP_SE[0..3]_BANK64 HP_SE[4..7]_BANK65 HD_SE[12..23]_BANK47 HD_SE[0..11]_BANK48 SPARE_U1_DIFF[0..7] SPARE_U1_[0..11] SPARE_U2_DIFF[0..7] SPARE_U2_[0..11] 1V8_U1 1V8_U2 IPMC_USER[0..7] ZONE1_HA[0..7] SERIAL_ID[0..3] (PWR_SEQ,CTRL_MEZZ,fFex) UZ_MASTER_JTAG[0..3] 3V3_BL 3V3_BL 1 ULTRAZED_GCK1_IN 40.08MHz 2 ULTRAZED_MUX_CLK_OUT PMBUS JTAG SYSMON DX SOM_RESET_IN_N SOM_PG_OUT CC_RESET_OUT_N SYSMON V USB_OTG CC_SDA/SCL UZ_SLAVE JTAG NC 1V8_BL 10k 1V8_BL 10k CC_INT_N 1V8_BL 10k PWR_SEQUENCING 3V3_BL UART CTRL_MEZZ FTDI UART1 MUX_I2C_UZ_SW1 1V8_U2 3V3_BL VCCO_HP64_1V8_U1 VCCO_HP65_1V8_U2 VCCO_HD47_3.3_VBL VCCO_HD48_3.3_VBL MGTAVCC_0.9V/3A MGTAVTT_1,2V/3A MGTRAVTT_1.8V/2A MGTRAVCC_0.85V/2A MGTAVTT_1,2V/3A 12V_UltraZED_12V/4.29A VCC_BATT UZ_SPARE_SE[0..11) 4 4 I:/fFEX_Document/Design/UltraZED/UZ_PWR_requires.bmp 12V_UltraZED_12V/4.29A MGTRAVCC_0.85V/2A I:/fFEX_Document/Design/UltraZED/UZ_PWR_requires.bmp MGTRAVTT_1.8V/2A MGTAVCC_0.9V/3A MGTAVTT_1,2V/3A MGTVCCAUX_1.8V/0.5A 1V8_U1 1V8_U2 3V3_BL 3V3_BL VCC_BATT 3V3_BL VCCO_PSIO_501_MIO 3V3_BL 4 2 8 12xdiff 12xdiff 24xdiff 24xdiff UltraZed PowerSupply 12V_UltraZED_12V/4.29A 1V8_BL SENSE_MGTAVTT SENSE_MGTAVCC SENSE_MGTRAVTT SENSE_MGTRAVTT IPBUS CTRL_MEZZ SSD m.2 PHY1_CTRL(6) RJ45 2diff 2 diff /SGMII) RJ45 DCS 2 diff /SGMII) PHY1 PHY2 IPBUS DCS RESET SW FRONT_RES MAC PHY3 2diff SPARE SSD_M.2_CLK I2C MULTIPLEXER RJ45 PHY2_CTRL(6) CTRL_MEZZ IPBUS PHY CTRL_MEZZ_DCS PHY CTRL_MEZZ SSD m.2 CTRL_MEZZ MAC PHY CTRL_MEZZ SPARE PHY3_CTRL(6) 2diff SPARE CTRL_MEZZ SPARE 2diff CTRL_MEZZ SSD m.2 CTRL 5 UART3 µUSB MIO(32,33,34,35) MCP3331A CTRL_MEZZ DUAL UART JC_FIXED_CLK3 3diff UZ_SPARE CLK USB_JTAG_D+/- JTAG U1 JTAG U2 UZ_MASTER_JTAG UZ_SLAVE_JTAG JTAG INTERFACE USB JTAG to JTAG CTRL MEZZ CPLD1 SPARE [0..11] CPLD2 SPARE [0..11] TCA9548ARGERQ1 SDC0 SDC1 SCD2 SDC3 SDC4 SDC5 SDC6 SDC7 SDC RESET_B MUX_FIREFLY_CH1 MUX_PMBUS_CH0 MUX_PROCESSOR_U1_CH2 MUX_PWR_STATUS_CH5 MUX_JC_CH4 MUX_SERIAL_ID_CH6 MUX_PROCESSOR_U2_CH3 I2C switch1 EN TCA9517BDGKR SDCB SDCA To CONTROL CPLD3 I2C switch2 EN TPCA9517BDGKR SDCB SDCA I2C_2_MUX To CONTROL CPLD3 VCCA VCCB VCCA VCCB To UltraZED I2C_UZ_MUX_SW1 2 2 2 2 2 2 2 2 2 2 2 2 2 MUX_FIREFLY_CH1 MUX_PMBUS_CH0 MUX_PROCESSOR_U1_CH2 MUX_JC_CH4 MUX_PROCESSOR_U2_CH3 CTRL_MEZZ I2C MULTIPLEXER I2C_MUX RESET (MIO43-SDA+MIO42-SCL) I2C MULTIPLEXER UZ UART0 IPMC USB C Mainboard FTDI UART1 MCP2221A USB MICRO I2C_2_MUX 2 CDBUS DBBUS USB_JTAG_I2C_MUX_IN 4 2 2 2 2 FTDI IPMC_UART 2 MicroSD MIO(44-51) CTRL_MEZZ MicroSD 4 4 4 4 UART0 UART1 UZ_UART0/1 UZ_UART1 USB C HSDP_TX0/TX1 HSDP_RX0/RX1 UART I2C DS2484 CH6 UART3_I2C UZ_UART0 3V3_UP 3V3_BL I2C_MUX_TEST_HEADER 2 2 2 2 2 CPLD3 RESET_I2C_MUX RESET_UART_MCP2221 UZ_RESET# 1V8 JX1/A2 UZ_RESET_LED JX1/C46 FTDI RESET RESET_FTDI FTDI POR FTDI POR RESET_PHY1 RESET_PHY2 RESET_PHY3 I2C SW1 ENABLE_3V3 I2C SW2 ENABLE_3V3 REST SW CPLD3 JX1A2 FTDI RESET#5_I2C_MUX RESET#6_UART_MCP2221 RESET#4_FTDI FTDI RES RESET#1_PHY1 RESET#2_PHY2 RESET#3_PHY3 RESET#7_UZ 1V8 FRONT_RES UltraZED UltraZED CH0 FTDI RES RESET#-FTDI JTAG_MUX1_SEL_3V3 JTAG_MUX2_SEL_1V8_U2 JTAG_MUX3_SEL_1V8_BL UZ_ SPARE [0..11] JTAG_MUX1_SEL_3V3 JTAG_MUX2_SEL_1V8_U2 JTAG_MUX3_SEL_1V8_BL I2C SW1 ENABLE1_3V3 I2C SW2 ENABLE2_3V3 JTAG_TAP1_SEL_3V3 JTAG_MUX1_SEL_3V3 JTAG_MUX2_SEL_1V8_U2 JTAG_MUX3_SEL_1V8_BL PHY1_CTRL(6) PHY2_CTRL(6) PHY3_CTRL(6) JTAG SPARE[0..4] SPARE[0..4] SPARE[0..4] SPARE[0..4] SPARE[0..4] SPARE[0..4] CPLD1 SPARE [0..11] CPLD2 SPARE [0..11] UZ_ SPARE [0..11] XC2C128-7CPG132I RES RES RES MUX_I2C_UZ_SW1 3V3_BL 2V5_BL 1V8_BL 1V8_U1 1V8_U2 POWER_OK ULTRAZ_SOM_PG 1V8_JC MAINBOARD PWR_SEQ 3V3 3V3 3V3 MAC SPARE I2C SW1 ENABLE_3V3 I2C SW2 ENABLE_3V3 I2C SW1 ENABLE_3V3 I2C SW2 ENABLE_3V3 UZ UART1 MIO32/33 MIO34/35 DP/DM 1V8_U1 1V8_U2 3V3_BL HEADER 2 x10 RESET#5_I2C_MUX CH1 CH2 CH3 CH4 CH5 MUX_PWR_STATUS MUX_SERIAL_ID To MAINBOARD INTERN PWR STATUS CH7 I2C GPIO 2 4 TCA9538PWR To CPLD2 MUX_I2C-GPIO_CH7 To MAINBOARD 2 Jitter Cleaner JITTERCLEANER SDC JITTERCLEANER SDC FIXED LHC JITTER CLEANER I2C 2 MICROCONTROLLER I2C switch3 EN SDCB SDCA VCCA VCCB SDC MUX_JC_CH7 GPIO PROGRAMMER MEZZ SEL0 I2C SEL1 SEL0 SEL1 To CONTROL CPLD2 To CONTROL CPLD2 VDD VDDA VDD VDDA VDDO VDDO VCC 3V3_UP 3V3_BL MUX_JC_CH7 JC FIXED SEL0 JC FIXED SEL1 JC LHC SEL0 JC LHC SEL1 RESET#5_I2C_MUX 1 1 To CONTROL CPLD3 To CONTROL CPLD2 TCA9517BDGKR JC_PROGRAMMER_EN To CTRL_MEZZ sda scl sda scl 2 jc_res_a jc_res_b JC_3V3 JC_3V3 JC_3V3 res CONTROL CPLDs FireFly CONTROL CPLD2 JTAG BANK3 VCCIO=1V8_U1 XC2C384_FTG256 FPGA CONFIG_CPLD1 CLOCK 1KHz GCK0 JTAG_CPLD SN74LVC1G14DPWR JTAG JTAG_3 SN65LVDS4 1.8V CMOS GCK1 GCK2 BANK1_3V3_BL VCCINT VCCIO1 VCCAUX CTRL_MEZZ 4K7 TDI,TMS,TCK,TDO JC FIXED SEL0 JC FIXED SEL1 JC LHC SEL0 JC LHC SEL1 1V8_CPLD VCCIO2 FPGA UltraZed RESETSW_CTRL_MEZZ Front VCCAUX_3V3_UP VCCAUX_3V3_UP CLOCK_MUX_SEL0 CLOCK_MUX_SEL1 FANOUT1_CLK_SEL FANOUT2_CLK_SEL FANOUT3_CLK_SEL FANOUT4_CLK_SEL FANOUT5_CLK_SEL FANOUT6_CLK_SEL FANOUT7_CLK_SEL FANOUT8_CLK_SEL FANOUT9_CLK_SEL FANOUT10_CLK_SEL FANOUT11_CLK_SEL FANOUT12_CLK_SEL FANOUT13_CLK_SEL FANOUT14_CLK_SEL 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 BANK4 VCCIO=1V8_U2 FPGA 32 32 VCCIO3 VCCIO4 1V8_U1 1V8_U2 3V3_BL 3V3_UP 3V3_UP BANK3 VCCIO=3V3_BL CLOCK 1KHz GCK0 SN74LVC1G14DPWR SN65LVDS4 1.8V CMOS GCK1 GCK2 VCCINT VCCIO1 VCCAUX 1V8_CPLD VCCIO2 BANK4 VCCIO=3V3_BL VCCIO3 VCCIO4 3V3_BL 2V5_BL 3V3_UP 3V3_UP 56 46 54 54 BANK2_3V3_UP BANK1_2V5_BL BANK2_3V3_UP 48 56 54 54 FF_RX_SEL,RES,INTL 3 U1_FF1 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 U1_FF2 U1_FF3 U1_FF4 U1_FF5 U1_FF6 U1_FF7 U1_FF8 U1_FF9 U1_FF10 U1_FF11 U1_FF12 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_TX_SEL,RES,INTL 3 FF_TX_SEL,RES,INTL 3 FF_RXTX_SEL,RES,INTL 3 FF_RXTX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 U2_FF1 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 U2_FF2 U2_FF3 U2_FF4 U2_FF5 U2_FF6 U2_FF7 U2_FF8 U2_FF9 U2_FF10 U2_FF11 U2_FF12 FF_RX_SEL,RES,INTL 3 FF_RX_SEL,RES,INTL 3 FF_TX_SEL,RES,INTL 3 FF_TX_SEL,RES,INTL 3 FF_RXTX_SEL,RES,INTL 3 FF_RXTX_SEL,RES,INTL 3 FELIX FF_RXTX_SEL,RES,INTL 3 3V3_BL 2V5_BL XC2C384_FTG256 UltraZED_IPMC_USER[0..7] CTRL_MEZZ_Spare[0..11] UltraZED_Spare[0..11] UltraZED_ZONE1_HA[0..7] UltraZED_IPMC_USER_3V3_UP[0..7] UltraZED_ZONE1_HA_3V3_UP[0..7] CTRL_MEZZ_Spare[0..9] CTRL_MEZZ_Spare[0..9] UltraZED_IPMC_UART[0..1] UltraZED_IPMC_UART[0..1] CLK_CTRL_2V5<0..19> JTAG_MUX2_SEL 36 53 42 28 8 16 18 JTAG_MUX2_EN/SEL 39 43 30 IPMC 54 8 16 18 43 CPLD1-2_Spare[0..11] CPLD1-2_Spare[0..11] 40 CTRL_MEZZ_Spare[0..11] to CTRL_MEZZ I2C SW3 ENABLE_3V3 44 JC_PROGRAMMER_EN 20 To CPLD1 To CPLD2 GPIO[1..8] I2C To CTRL_MEZZ TCA9538PWR I2C_I/O EXPANDER BUTTON BUTTON BUTTON PUSH[1..3] FF ADDRESSING LevelTrans LevelTrans I/O JTAG MASTER TCK TMS TDI TDO TMS TCK TDO TDI 4x10k TDI TDO TMS TCK XCVU13P TDI TDO TMS TCK XCVU13P U1 U2 USB_C RX_P/N TX_P/N 4 4 TO FPGAs D+ D- USB_JTAG_I2C_MUX_IN MAINBOARD JTAG BOUNDARY TEST MEZZ TDI TDO TCK TMS LEVEL TRANSLATOR TMS TCK TDI SN74AVC4T774 TDO TCK TMS TDO TDI 39R LEVEL TRANSLATOR TMS TCK SN74AVC4T774 TCK TMS 39R U1 U2 TDO TDO OE* OE* TDI TDI LEVEL TRANSLATOR TMS TCK TDI SN74AVC4T774 TDO TCK TMS TDO TDI U1 OE* JTAG_SLAVE TMS TCK TDO TDI D1 D2 C1 C2 UltraZed-EV CTRL-MEZZ PORT1 PORT2 PORT4 1 3 5 JTAG MASTER USB_C RX_P/N TX_P/N D+ D- FTDI TDI TDO TCK TMS HEADER TAP1 VREF SELECT ZYNQ TDI TDO TCK TMS JTAG BANK47 JTAG CTRL MEZZ - JTAG INTERFACE MUX or JUMPER JTAG_2 TCK TMS TDI TDO TMS TCK TDO TDI TDI TDO TMS TCK XCVU13P U1 U2 USB_C RX_P/N TX_P/N 4 4 TO FPGAs D+ D- JTAG_MUX1_SEL JTAG_MUX2_SEL MAINBOARD CTRL MEZZ TAP2 USB_JTAG TDI TDO TCK TMS JTAG HEADER CTRL_MEZZ D- Digilent_SMT2_NC D+ USB TCK TMS TDI TMS TCK TDO TDI MAIN_TMS UltraZED_I/O_TMS MAIN_TCK UltraZED_I/O_TCK MAIN_TDO UltraZED_I/O_TDO MAIN_TDI UltraZED_I/O_TDI HEADER 4k7 4x10k 4x10k USB_JTAG_I2C_MUX_IN TDI TDO TMS TCK XCVU13P 5 TDO TMS TCK 1 2 3 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 TAP1 4x10k SEL 0 = SxA to Dx SEL 1 = SxB to Dx SEL 0 = SxA to Dx SEL 1 = SxB to dx 19 CPLD3 1V8_BL 4 3V3 Master Slave MUX1 MUX2 MUX3 6 7 8 TDI TCK TMS TDO TDI TCK TMS TDO 3 TDO 2 1 TMS TCK TMS TCK TDO TDI 1V8_U2 1V8_U2 3V3_BL SEL 0 = SxA to Dx SEL 1 = SxB to Dx JTAG_MUX3_SEL 1V8_BL JTAG_MUX3_SEL CLOCKING U1 U2 FELIX CML_DC LHC Cleaned multiple clock 7 7 8 9 8 2 2 1 3 4 14 13 13 14 15 19 19 20 21 20 Bank 65 Bank 65 Recovered clock_CML_AC Bank 65 Bank 65 Controller UltraZed FPGA XCZU7EV-1FBVB900E FELIX xtal refclk Inputs xtal reflck FELIX FELIX FELIX FELIX LHC Cleaned multiple clock Control Control CPLD Control Control MGT1_156.25MHz MGT2_240.48MHz MGT3_LHC_CLEAN_CLK MGT4_LHC_CLEAN_CLK 1 16 LVDS Recovered clock LVDS Recovered clock 1 2 3 4 1 2 3 4 1 3 CPLD TEST TEST CPLD TEST CML_DC CML_DC Recovered clock_CML_AC FIXED GCK1_LHC_CLEAN_CLK CML_DC LHC TEST FELIX FELIX 40.08 MHz Zero delay loopback LVDS_AC LVDS_AC Independent clock CPLD3 LVDS_AC LVDS_AC TEST EMCCLK EMCCLK CMOS LVDS 1.8 CMOS Configuration CLOCKs SN65LVDS4 SN65LVDS4 30.00 MHz 22 10 HSDP / spare HSDP / spare LVDS_AC LVDS_AC CPLD2 CPLD1 CMOS CMOS LVDS LVDS LVDS LVDS_AC LVDS_AC CML_AC CML_AC CML_AC CML_AC 156.25 MHz 2 TTC TTC 4 LVPECL LVPECL CPLD3 JC_CH7 A0 1 A0 JC_CH7 0 LVDS_AC SEL0 CPLD 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 6 5 1 2 6 5 GCK2 1 2 3 4 5 6 GCK1 GCK2 GCK2 GCK1 Output CML_DC Output MGT1 Output Output TEST NA CPLD3 CPLD3 CPLD3 CPLD3 CPLD3 CPLD3 CPLD3 CPLD CPLD CPLD CPLD3 LVDS_AC GTH quads MGTRefClk AC coupled 224 225 227 224 225 226 227 226 CML_AC MGT5A_LHC_CLEAN_CLK MGT5B_JC_FIXED_ALT_CLK MGT5A_LHC_CLEAN_CLK GC JX1 B11/12 P/N CML_AC 6 4 2 0 7 5 3 1 MGT2 MGT3 MGT1 FIXED MGT1 MGT4 Out CML_AC FIXED LVDS 1.8 CTRL_MEZZ GCK1 CLK_MUX 2 7 8 9 JC_FIXED_CLK3 5 6 7 8 9 7 9 0 8 6 5 2 4 1 3 GTR quads AC coupled 505 505 505 505 0 1 2 3 FIXED FIXED CML_AC CML_AC 10 11 Spare_CLK2 Spare_CLK1 Spare_CLK3 MGT2 clock 240.48 MHz MGT1 clock 156.25 MHz CTRL_MEZZ clock 156.25 MHz Interlaken alternative 128.9062 MHz Configuration U1 clock 88 MHz Configuration U2 clock 88 MHz UZ_GCK1_IN 40.08MHz UZ_MGT3_IN 320.64 MHz UZ_MGT1_IN 156.25 MHz UZ_MGT2_IN 240.48 MHz UZ_MUX_CLK_OUT UZ_MGT1_IN 156.25 MHz UZ_MGT4_IN 80.16 MHz IN OUT OUT OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SEL1 SEL0 SEL1 UZ JC fixed CLK4_IN 100 MHz UZ JC fixed CLK3 IN 125MHz 0 1 2 3 4 5 6 7 8 9 MGT5B JC fixed ALT_CLK 128.9062 MHz UZ JC fixed CLK6 100MHz UZ JC fixed CLK5 100MHz 1 2 3 4 5 6 7 8 9 10 11 UZ JC fixed CLK3 IN 125MHz UZ JC fixed CLK4_IN 100 MHz UZ JC fixed CLK5 100MHz UZ JC fixed CLK6 100MHz 3 4 5 6 MGT5 9 10 11 12 MGT5 MGT1 15 16 17 18 21 22 23 24 CML_DC VDDO 1.8V_U2 VDDO 1.8V_U1 SN65LVDS4 SN65LVDS4 JC_FIXED_CLK3 3 4 6 5 SI591EB SI591EB SI530FB Bank 71 Bank 71 CPLD3 CMOS SN65LVDS4 Mezz JX1 B15/16 JX2 D5/6 SE_GC UZ_GCK2 OUT MGT5 MGT5 4 4 4 FF1 U1_1 4 4 4 FF2 U1_2 4 4 4 FF3 U1_3 4 4 4 FF4 U1_4 4 4 4 FF5 U1_6 4 4 4 FF6 U1_7 4 4 4 FF7 U1_8 4 4 4 FF8 U1_9 4 4 4 4 4 4 4 4 4 4 FF9 U1_5 FF10 U1_10 FF11 U1_11 FF12 U1_12 U1 4 4 4 R1 U2_1 4 4 4 R2 U2_2 4 4 4 R3 U2_3 4 4 4 R4 U2_4 4 4 4 R5 U2_6 4 4 4 R6 U2_7 4 4 4 R7 U2_8 4 4 4 R8 U2_9 4 4 4 4 4 4 4 4 4 4 T1 U2_5 T2 U2_10 U2_11 RT2 U2_12 U2 UltraZed U1 U2 High Speed Links 4 4 4 4 AC AC AC AC 2 2 HIGH SPEED JTAG 1 2 2 1 1 1 1 1 1 1 1 AC AC AC AC USB_C AC AC AC AC Inter-FGPA connectivity CTRL MEZZ HSDP 4 LOW SPEED 4+4 FireFly_RXTX 4+4 FireFly_RXTX RT1 4+4 FireFly_RXTX 4+4 FireFly_RXTX 4 4 4 4 FELIX Quad 224 Quad 225 Quad 226 Quad 227 SPARE (MAC SGMII) 2 2 4+4 FireFly_RXTX RT5 Z_1 4 4 IPBUS DCS SSD GTR 505 CTRL Mezz 2 2 2 spares 4 4 SPARE Rx/Tx Rx/Tx Rx/Tx Rx/Tx Rx/Tx U1_CTRL_HSDPRX_O_P/N U2_CTRL_HSDPRX_O_P/N U1_CTRL_HSDPTX_O_P/N U2_CTRL_HSDPTX_O_P/N U1 XCVU13PFLGA2577 BANK65 EMCCLK D4..D9 GC1 DOUT_CS0_B I2C FCS2_B CSI_ADV_B GC2 GC3 U1 XCVU13PFLGA2577 BANK71 GC I/O U1_SPARE_P/N<8..1> U1_SPARE_GC1_P/N VRP 240 DCI U1_EMCCLK_P U1_EMCCLK_n U1_D4..9 U1_Dout U1_I2C U1_FCS2_B U1_CSI_ADV_B VRP 240 DCI GCK1 GCK2 RECOVERED_CLK SN65LVDS4 U2 XCVU13PFLGA2577 BANK71 GC I/O U2_SPARE_P/N<8..1> U2_SPARE_GC1_P/N VRP 240 DCI I/O U1_SPARE<1..11> U1 XCVU13PFLGA2577 BANK0 INIT_B PROG_B M2 CCLK D0..3 RDWR_FCS PUDC_B U1_INIT_B U1_DONE U1_PROG_B U1_M1 U1_CCLK U1_D0..3 U1_RDWR_FCS U1_PUDC_B U1_DXP MT25QU02GCBB8E12-0SIT SPI NOR FLASH MEMORY U1_D0..3 U1_CCLK U1_RDWR_FCS 1V8_U1 MT25QU02GCBB8E12-0SIT SPI NOR FLASH MEMORY U1_D0..3 U1_CCLK U1_RDWR_FCS 1V8_U2 SN74AVC1T45 DONE 1V8_U1 3v3 B A D2=4k7 D3=4k7 2k4 M0 M1 U1_M0 U1_M2 POR_OVERRIDE VCCADC GNDADC VP VN VREFP VREFN DXP VBATT RSVDGND 1V8_U1 VCCAUX_U1/U2 DXN U1_DXN VCCINT_U1 U1 XCVU13PFLGA2577 BANK0 INIT_B PROG_B M2 CCLK D0..3 RDWR_FCS PUDC_B U2_INIT_B U2_DONE U2_PROG_B U2_M1 U2_CCLK U2_D0..3 U2_RDWR_FCS U2_PUDC_B U2_DXP SN74AVC1T45 DONE 1V8_U2 3v3 B A M0 M1 U2_M0 U2_M2 POR_OVERRIDE VCCADC GNDADC VP VN VREFP VREFN DXP VBATT RSVDGND 1V8_U2 VCCAUX_U1/U2 DXN U2_DXN VCCINT_U2 D2=4k7 D3=4k7 2k4 FPGA CONFIG_CPLD1 FPGA CONFIG_CPLD1 to CTRL_MEZZ to FPGA CONFIG_CPLD1 U2 XCVU13PFLGA2577 BANK65 EMCCLK D4..D9 GC1 DOUT_CS0_B I2C FCS2_B CSI_ADV_B GC2 GC3 U1_EMCCLK_P U1_EMCCLK_n U1_D4..9 U1_Dout U1_I2C U1_FCS2_B U1_CSI_ADV_B VRP 240 DCI GCK1 GCK2 RECOVERED_CLK SN65LVDS4 I/O U1_SPARE<1..11> to CTRL_MEZZ to FPGA CONFIG_CPLD1 TDI TDO TCK TMS JTAG I/O MUX or JUMPER HEADER or USB Interface JTAG MASTER JTAG_1 TCK TMS TDI TDO TMS TCK TDO TDI 4x10k TDI TDO TMS TCK XCVU13P TDI TDO TMS TCK XCVU13P U1 U2 USB_C RX_P/N TX_P/N 4 4 TO FPGAs D+ D- USB_JTAG_I2C_MUX_IN MAINBOARD JTAG BOUNDARY TEST MEZZ TDI TDO TCK TMS HEADER LEVEL TRANSLATOR TMS TCK TDI SN74AVC4T774 TDO TCK TMS TDO TDI 4x10k 39R LEVEL TRANSLATOR TMS TCK SN74AVC4T774 TCK TMS 39R LEVEL TRANSLATOR SN74AVC4T774 TDO TDi U1 U2 TAP1 TAP2 TDO TDO VREF OE* OE* OE* TDI TDI LEVEL TRANSLATOR TMS TCK TDI SN74AVC4T774 TDO TCK TMS TDO TDI U1 OE* LEVEL TRANSLATOR SN74AVC4T774 TDO TDO OE* JTAG_SLAVE TMS TCK TDO TDI D1 D2 C1 C2 UltraZed-EV CTRL-MEZZ PORT1 PORT2 PORT3 PORT4 1 2 3 4 5 6 7 8 A B C D JTAG MASTER JTAG_SLAVE Since Version 6.2.2 text objects can contain more than one line, which will not be processed correctly with this version.