30.7.
4 more input bitfiles, all const 0 to backplane, except const 1 to FIO22.
Outpot settings are DCI, CMOS15 at 2,12,16mA

29.7.
ace-out-intest-1.bit : FIO bit number n is permanently set to '1' 
when n is written to the threshold low register of the input module under test.

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28.7.
jet firmware comparison:
firmwares used: JTAG versions, date marked from your web space

data from left : ramp generator enabled.
core: expected 0
no right hand neighbour, inputs floating...

test version as of Jul24,09:29
full production version as of Jul24,09:25