All JEM1 processors will be configured from STM CFI-type parallel flash memory. A total of two chips (ie. currently 128Mbit) is considered enough to allow for multiple configurations of all processors. The chips are to be flashed by VME and will therefore not be socketed. BGA packages are preferred, since any upgrade would require proper re-work facilities, even if TSOP packages were used.
The configuration sequencer will be located in the control FPGA which accesses the parallel flash memory via user I/O pins. The control FPGA itself needs to configure from non-volatile memory upon power-up. To this end three configuration methods are supported.
1) Xilinx 'serial' PROM XC18V04 PC44C. A single Xilinx PROM is sufficient to carry the configuration for a XC2V1000 FPGA. The Xilinx PROM will be socketed and it acts as a fallback solution only in case the concept of parallel CFI configuration fails. Please note that the parallel configuration mode of the Xilinx PROM might be used, if it simplifies board layout or control circuitry. Since all signal lines are fed to the (normally unused) socket only, no multiplexers should be required to select a given configuration mode. The use of parallel slave mode with a free-running external crystal clock (f/2=20MHz, via CPLD) is envisaged so as to avoid config clock and M-pin switching (http://direct.xilinx.com/bvdocs/publications/ds026.pdf, fig.7b, p.12). The Xilinx flash ROM will be loaded via JTAG on a separate header. For Boundary-Scan tests there should be jumpers? provided to connect the scan port to the chain.
2) VME-controlled byte-wide configuration through the CPLD. The CPLD will disable itself after successful configuration of the control FPGA. The control FPGA will take over the VME bus handling once it is configured. The successful configuration of the control FPGA is signalled to the CPLD through a dedicated user pin of the FPGA. This line carries an external pull-up resistor. The CPLD has two write-only registers (or a single register with 8+1 width?) to allow for byte-wide configuration and for a configuration reset of the control FPGA. The CPLD and the FPGA should be wired such that the control FPGA is able to reset itself (might require the CPLD to stretch the reset command??) and start afresh with the CPLD taking over control. This configuration method is intended for the initial setup in the lab only to avoid frequent re-programming of the CFI-type flash memory.
3) The base line configuration is done via the CFI-type flash memory. While the memory write access is possible through the once-configured control FPGA only due to the complicated programming algorithm, the memory read access is sufficiently simple to allow for the sequencer to be located in a CPLD. After power-up / reset the flash memory is in array read mode and it can be read-accessed like any random access EPROM. The CPLD generates an incrementing address and and writes the data to the byte-wide FPGA parallel configuration port (slave mode). 16-bit mode and page-read facility should not be used when under CPLD control. Not using the page read mode the minimum latency is 5 ticks (>110ns). Once the FPGA comes up, and the CPLD is disabled, the port width and the memory timing might be changed. However, 16 bit access is not any faster, if page read / buffer write mode is used anyway. Address 0 (block 0 !) should contain status information and the configuration area should start at a higher address (how many status words required? check protection mechanism ). The CFI flash control will require approximately 30 user I/O (address & control) on the CPLD and on the FPGA (VQ100 large enough?).
The 3-way configuration scheme requires the memory address lines to be driven by both the control FPGA and the CPLD. The data bus (8/16 bit with correct handling of a0) is connected to the CFI flash, the Xilinx flash, the VME port, the CPLD (few data bits only), and the control FPGA. The control of bus drivers an data ports needs to be exercised by both the FPGA and the CPLD. Bus hold / pull-up might be required to keep the system stable when switching the bus master (CPLD/FPGA). The flash addresses cannot be directly mapped into the VME address space, since the total per-JEM space is 512K only. Therefore the addresses are connected to the CPLD and the FPGA only and both devices need to negotiate their use.
The availability of XC2C64-7VQ100C needs to be checked *now*. This device carries 64FFs only. Since quite some FFs are required for counters (address, timers) most other operations need to be asynchronous to free the FF resources. Otherwise a larger device (minimum 128) would need to be chosen XC2C128 might be preferred anyway so as to benefit from clock division option (will require the incoming clock to be routed to two global clocks so as to have two frequencies available on the global network) (later upgrade if not available now).
CPLD I/O use:
for selectmap configuration handshake (the data port overlaps with the VME port and is not feed through the CPLD)
VME bus driver handshake
separate enables for the two data port chips
write?
for flash access:
total: 25 lines + data lines ?
some of the flash memory signals might either be connected to to the CPLD or pulled up/down to default values when not driven by the FPGA: