The baseline control module will
comprise of the CAN controller and a minimum functionality VME and
configuration controller. Also some general control functions will be implemented
on the control module. Full VME functionality will be available to the JEM only
after successful configuration of the sum FPGA.
Currently a test version of the
control module is under way which will not carry the CAN circuitry. VME,
configuration, and general control circuits will however, be fully functional.
All logic is implemented in a single
small CPLD (xc2c64-vq100c/xc2c128-tq144c). To allow for hot-swap operation of
the JEM the following rules apply:
The VME buffers are driven to OFF /
WRITE (into the JEM). DTACK driven to off. Switched supplies
driven OFF. Local linear regulators for CPLD 3.3V and 1.8V.
Power
control and sequencing
Use a single pin of CPLD to control Vcc chain. Use external pull resistor (provide pull-up and
pull-down option)
Use DCok and
remoteON functionality of selected step-down regulators.
Sequence: We ignore the
recommendation on applying vccint first since it
relates to master configuration ONLY
First VCCaux
3.3V
Then vccint
1.5, Vccout 3.3V
TTC
control:
Hard-wired TTC ID generation:
JEM ID is 010c nnnn
000011 (c = crate number: GeoADD 4, nnnn=GeoAdd 3 downto
0) (GND,3.3V, geo (all via 1k)
Mapped to SubAddr<5:0>,
Dout<7:0>
Reset_b: pull-up (automatic startup upon pwr-up) to CPLD and Sum?
Debug mode, automatic changeover:
P/D: 0: pull-down (to sum?)
Clk_sel: 1: pull-up (to sum?)
VME
Single small CPLD connected to top
and bottom level addresses, data, ds, write, dtack. Sum dtack through route
Configuration
Check L1tr rules on re-configure and
configuration select for ACE. Decide on CPLD control for ACE vs. Sum FPGA
control for ACE.
Run TCK through standard CMOS buffer
or clock fan (eq. 244, series terminators!)
ACE reset to pull-up and pull-down
and CPLD pin.
5 bit GeoAddr
to sum, CPLD, TTC-Rs