JEM1 problem sheet

Wrong bit order on Sum config port Xilinx: bit 0 = MSB

Hi/Lo port muxing for configuration does not work

No pull-ups for TTC P/D and clocksel à will require to reset DLLs after setting the signals in Sum configuration

No direct Sum FPGA access to Geoadd à need to route through spare sum-control lines

Defective input channels:

(from0)

W4

H4 p

E6

D2 p (inst)

A6 bit 6 always ‘1’ (x40) P

Cern 23 aug - 8 oct

5,4,6,7,3,2,8,9, --duplicated, unused

z 10,18,1,17,20,22,15,13,

x 11,19,0,16,21,23,14,12,

h 6,8,5,3,10,18,1,17,

g 7,9,4,2,11,19,0,16,

f 15,14,20,21,13,12,22,23,

e 5,4,6,7,3,2,8,9,

d 10,18,1,17,20,22,15,13,

c 11,19,0,16,21,23,14,12,

b 6,8,5,3,10,18,1,17,

a 7,9,4,2,11,19,0,16,

v 20,22,21,23,15,13,14,12