Test programme to be followed after each f/w modification and before every RAL / beam test

Single-JEM tests:

1) DSS loaded with 511-wrap binary counter. Check test pattern error counters. Confirm that phase detection is working. Repeat for all connector blocks. Bottom one requires adapter !

All other checks are done with the on-line software and can be run off the playback memories to operate all channels:

2) check energy sums captured in spy memories

1) generate l1a and check ROC spy. The spy format is identical to the ROD G-link format and existent online/simulation s/w can be used. As long as we do not have the L1A generating DSS we will use playback -> ROC spy mode with a L1A generator (16 k*1bit) internally in the sum FPGA. It is synchronised via broadcast command (pointer reset). This setup will also run with DSS and with several JEMs if all are loaded with same L1A pattern.