So as to speed up the JEM1 design process, to allow for a maximum of spare resources, and to avoid signal and bank fragmentation, only point-to-point connections between the major components are used.
(A 1.2V supply should be considered to allow for an upgrade of the daughter modules. Separate Vcco 1.5V supply for main processor to change over to 1.2 V logic ? Is VII 1.2V I/O compatible (see datasheet DC characteristics!) )
Connect VRN /VRP on each bank individually, VRN to Vcco of that bank, VRP to GND.
Naming convention: Daughters are named R,S,T,U from bottom to top. The channels are allocated to the daughters as follows:
R (VAB),S(CDE),T(FGH),U(WX-) from bottom to top. The top channel of daughter U is unconnected.
On the schematics do not name pins according to function, but rather to the devices they connect to : a given line from daughter R to the Sum FPGA could be named Sum_R(13). Allocation to functionality will be done inside the FPGA.
All backplane signals from and to the input daughters will be routed identically for all 4 modules apart from the signals not available on module U. Signals to the Jet and Energy processors can be connected in any order. Decide whether the JEM0 backplane pinout is kept. For the LVDS inputs it is important to observe the cable map. Signals for neighbouring phi bins run on the same cable (check w. JEM0).
Signals:
special tracking:
We assume that generally test headers are not required. Measurements are possible with an interposer to the input daughters at any time.
provide some test points (vias only) at receiving ends of signal lines for timing checks and signal integrity ? DCI reliable?
Decide on G-link mounting... Dual mount option? daughter / on-board?
run sum processor differential output line near the line drivers. use caps as jumpers.
TTC receiver chip (Maxim) on backplane, another one on inputs to daughter? 100R
2 * G-Link line driver EP89 with SHORT 50R track to Lemo
CAN PHY located near backplane
temperature converters MAX1668 (SMB bus) 2 chips for inputs and main, ROC pullups
to 3.3V ? Vcc 3.3V?
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2313/ln/en
2 * MAX6683 (Vcc=3.3V) for voltage monitoring 1.5, 1.8, 2.5, 3.3V analog,
3.3, 5.0 V
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3161/ln/en
X33 : 33 MHz crystal clock for SystemACE
VME data buffers 2x8bit : R/W directly connected to VME--, the 2 enables to control CPLD
VME address and control buffers : permanently enabled
DTACK tiny-logic inverter open drain http://focus.ti.com/lit/ds/symlink/sn74lvc3g06.pdf ? (3.3V, channels paralleled) close to backplane
front panel LEDs via CPLD, serial link from ROC, possibly from main, too?
Front panel clock monitor from clock mirror (on G-link daughter?)
each:
24 LVDS pairs
45 jet backplane pins
60 pins jet
69 control pins allocated now to 36 pins Energy Sum and 33 pins control/clock. The sum pins on module U remain unconnected. Net names do not distinguish control and Sum pins
There seems to be *no* 3.3V clock available check pinout!. --> we need to have resistor divider and run into a 1.5V GCLK line !
6 pins geo-add 3.3V
configuration pins 3.3V: cclk,din,dout,d1,done
3.3V INIT_B : wire-or bus, choose high-impedance pullups !, allow for breaking the bus on main board (pre-wired solder jumper) check for alternative routing via cpld
PROG_B to CPLD
4 pins link lock loss
2 temperature sense pins
2 pins slot ID encode: R=0,S=1,T=2,U=3
daughter version 3 pins grounded on current daughter module
2 JTAG chains (one with TRST)
No M-lines (pulled up internally, slave serial)
HSWAP_EN pullup, pwrdwn open
We might provide the footprint for another samtec connector for a revised daughter module to carry 1.2V and spare signals.
either from Jet processor 3.3V bank or separate CPLD (3-wire bus: clock,data,frame) set CPLD outputs to Z while shifting through (frame to GTS) some signals need to be displayed before configuration is up. Minimum: done LEDs. Do we want to display separate config success line from Sum FPGA ? needs to control the VME CPLD anyway.
G-links either on daughter or main board. Socket required for clock clean-up in case of G-link replacement:
differential pair out and each back to GCK (Sum,Jet)? 3.3V bank
route differential pair from each processor to close the PECL driver. use caps as jumper.
http://www.xilinx.com/isp/systemace/systemacecf.htm
capacitors: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11991
processor control is generally via Sum FPGA, except the pins required for ACE startup: CFGADDR,CFGMODEPIN
The pins connected to Sum FPGA should be connected to the CPLD in parallel, resources permitting. just in case.
3.3V on both rails and on compact flash card. connect flash chip and ACE
(CF-lines) 1:1 except:
VS1,VS2,WP,BVD1,BVD2 INPACK -- do not connect
IORD ,IOWR pullup5.1k
CSEL pulldown 1k
RDY/BSY to CPLD? pullup.
CFRSVD pull-up 5.1k
RESET : to CPLD ? ACEdoc p.37 : pulldown 1k
CFGADDR(2:0),CFGMODEPIN to CPLD
CFGPROG to CPLD
CFGINIT bus; allow for breaking it. CPLD? pre-wired solder jumper?
POR_BYPASS, POR_RESET to CPLD? no! won't work for config delay of CPLD
POR_TEST do not connect
STATLED (yellow? is it activity?) , ERRLED (red) : LED via 180R, to 3.3V to front panel (via ROC?)
CLK, RESET, MPCE, MPWE, MPOE, MPBRDY, MPIRQ ? connect to CPLD
MPA06:00 => VME_ADDR 7:1; VME addresses start at 1
MPD => VME data lines
CFG JTAG connect TDI/TDO to FPGA chain, TMS and TCK: bus
TST JTAG TDI/TDO separately ? to front panel connector, bridge there for board
scan. TMS and TCK (and TRST) : separate bus
according to CP schematics. Spare I/O-port (16 wide?) to Sum FPGA or Jet. sense all voltages (use same pinout as CP) To allow for a firmware update via VME, feed the CMOS-level RS232 line to the Sum FPGA or Jet . Caution: 5V signals use series resistors throughout.
no DIP switches, please. (CPLD/solder jumper) Check connectivity...testmode?
http://www.ep.ph.bham.ac.uk/user/staley/schematics/sheet28.pdf
Some functionality might be taken off the Control CPLD :
TTC ID setting (resistors near TTCdec) 16 bit derived from full geo address
most likely xc2c128 tq144 or '64tq100 we might try to export some signals to the TTC control CPLD
route all signals to Sum as well to take over after configuration complete except CFGADDR and CFGMODEPIN which are used in unconfigured state only
Connects to SystemACE(10), VME (50 incl geo-in), board version (3),board SN(6) ? geo out 6 VME control ~10 spare to FPGA ~16 input version 12
Connects to all VME-- lines, SYSRESET to a GSR line. 2 clocks : X40 and X33 to global clock pins.
4 lines JTAG for config download to FPGAs (via front panel connector)
XC2V2000-4BF957 624/608 pins (VRN/VRP)
Use all VRN/VRP in each bank
banks: 0:70 1:70 2:82 3:82 4:70 5:70 6:82 7:82
bank 4 : 3.3V. Bank 5 3.3V on Sum, 2.5V on Jet
GCLK 0P-3S in bank 4, 4P-7S in bank 5
GCLK 0S-3P in bank 1, 4S-7P in bank 0
check for meaning of S/P
clock switch? failsafe clock PLL? on socket?
do not connect PWRDWN_B ( nor HSWAP_EN ?)
M-pins: allow for JTAG, serial slave, selectmap slave. Other pins hard-wire (how on inputs?)
feed M to control CPLD !
PROG_B to CPLD
M, INIT, PROG_B, DONE, CCLK to ROC
RDWR_B, CS_B, BUSY, D7:D0 to ROC, use for VME equivalent.
pin budget:
Bank 4 3.3V : 70 pins : configuration (from Sum) and G-links and up to 4 clocks (from TTC/mirror),
(remainig 3.3Vpins might be used to drive front panel LEDs)
Bank 5 2.5V : 70 pins : configuration, 25 JMM, (also LEDs ? spares to Sum?)
Banks 0,1,2,3,6,7 : 1.5V 468 pins
jets (bpl+inp): 385
remaining to sum processor: 83 pins including 43 VME lines, TTC, 1.5V clocks
required:
2.5V : 1 bank 70 pins SMM and links to Jet (incl. Jet config, clocks to Jet)
3.3V : 3 banks ~200 pins including b4 and b5 (configuration pins, 8 clocks) : G-link, ACE, CAN, VME bus
1.5V : 4 banks ~ 300 pins
Input version number 4* ? any voltage? pull-ups? check for other spec. pins, which configs?
Available:
2.5V : 1 bank b0 or b1 : 70 pin this will cost us 4 clocks on Sum chip.
no 1.5Vclocks required -->
3.3V : 3 banks b4 and b5 and one of b0/b1 : 210 pins
1.5V : 4 banks all of b2/b3/b6/b7 : 328 pins
Detailed list:
1.5V : input 3*36+4*33 = 240 + jet 83 -->323 (max)
3.3V :
G-link 23
signal pair 2
VME 49
VME bus driver handshake + spare to CPLD 16 min
CAN 16 spares ? --> jet
ACE ~6 ?
TTC/clock 47 ?
JTAG to update CPLD 4
input version: 4*3=12 any voltage even mixed. set resistors appropriately
so far ~160 !
clean clockin/out pairs? to header, w. 3.3Vsupply. also single ended?
configs to inputs Din, dout (neither init nor program_B, nor m-lines), cclk,
??
m-lines need to be on CPLD or resistor-pulled to ACE config (do m's matter for
Jtag config?)
FPGAs via ACE. ACE test port separately to front panel. also config port connected via header(internal?)
pullups are required on open JTAG lines (check which)
All devices: wire-OR INIT_B with pullup to 3.3V (is that ok?)
Program_B drive common via CPLD for ACE config. Individually by VME.
On Sum parallel configuration on banks 4,5 at 3.3V. overlap with VME data port. To allow for 16 bit access control VME data buffers (and CPLD internal 3-state) byte-wide and re-map in CPLD. Pulldown on parallel configure pins. use BUSY on an out-only port (G-link?)
all Sum config lines to CPLD, the others via Sum, except program_B
use controlled cclk selectmap slave configuration on sum fpga !
http://www.xilinx.com/publications/products/v2/ug_pdf/ug002.pdf p 276
The config/control lines that are run via Sum will require pull-ups/downs to set the behaviour before Sum powers up. This is required due to the common init line!
Jet: configure from Sum parallel 3.3V/2.5V
Serial configuration and compressed VME on inputs
3* SN74LVT18512
B-Port 25R to JEM, A-Port to backplane
1 data buffer R/W, latched, registered (see below) byte-wide OE control on B port, word wide control on A-Port
1 address buffer (A1-A18) registered rather than latched???
1 high address buffer permanently enabled, A->B static : A19-A23, Write, SYSRESET, DS0, ~8 clocks, geoaddress?
Buffer controls: OEbar, LE (transparent=H), CLK rising
Latch seems transparent with LEA=1? we want to freeze data during dtackbar=0 ? need non-inverting dtack driver or separate output on CPLD --> skew? are we sure about latching so we dare direct connect?
for write and for the addresses during configuration time we prefer to clock into the buffer with the board select signal. Transparent latch would be faster but we want to keep internal signals valid after DS0 vanishes. forward the data to the next pipeline stage upon DTACK, When the FPGA takes over control we might wish to change to transparent latch mode or non-latched mode. --> control LEAB and CLKAB separately by CPLD. We can probably wire all data and address controls together???
DS0 to DTACK min. 30ns
-> WE NEED A DELAY CHIP:
VME CPLD receives DS0 and delayed DS0 and generates dtack (DS0 .and. DS=_DEL) we connect internal dtack to latch enable
Address high buffer: alway
can we use the bus driver latch facility to speed up VME?
latch internal address and data (for read access) on DS0*select and send DTACK immediately (async). is delay enough or do we require delay unit? bus driver+ CPLD pin-pin
for write: latch on dtack (transp latch?)
VME bus routed to CPLD and Sum in parallel !
DTACK requires pull-up or down (check polarity)
2.5V linear, to one bank of sum and jet
all pins to Sum FPGA, TTC-CPLD below daughter for setting ID via resistors. connect to geo lines, possibly do geo relay and VME board select / buffer control, handle m-lines in this device.
run geo-address through main processor. No need to buffer on backplane.
don't forget TTC-ID generation via resistors (separate pins??)
read input version registers into sum processor.
route unused pins of Sum and Jet FPGA to 2.54mm through-hole headers. Will not be assembled on final modules.
So as to allow for a later changeover to 'G-link' signal generation inside the processors we need a stable supply of a high-frequency clock. This could easily be generated in a LVDS serialiser with a 010101 pattern supplied to the parallel pins. If, however, we wish to run in the 16-bit mode, will have to generate a 200 or 400 MHz frequency which would require jitter cleanup if it came from DCM clock synthesis (150ps RMS required! ). We should run a LVDS pair (terminated either end) to both processors. also single ended base frequency supply single ended (3.3V) is required (from both processors) We might need to put circuitry on a socket if we cannot decide on jitter cleanup now.. terminate pairs by resistor
We might try to route pairs of signal pins from the SMM/JMM ports to backplane pairs to allow for a later changeover to differential transmission, should the need for higher merger bandwidth occur. Signal tracking single ended, 60R as usual. one pair might be a GCLK pair, if available.
while for the FPGAs the pinout is chosen to the needs of the layout, CPLDs need to be targeted with the near-final code to find out possible pin allocation !!!
dual function pins:
special use:
D7:D0 configuration lines and VME port D7:0
CS_B used for config and VME
RDWR_B, used for config and VME
BUSY/DOUT,
INIT_B : breakable bus and/or CPLD w. open drain?
GCLKs check which ones are required for clocks
VRP, VRN connect to GND Vcco
use as ordinary pins: ALT_VRP, ALT_VRN, VREF
dedicated pins:
CCLK,,DONE : to CPLD on sum processor, to Sum processor on other FPGAs Done pullups? not absolutely required
PROG_B to CPLD (|| FPGA for other FPGAs) (pullups?)
M2:0 to CPLD on both processors
HSWAP_EN internal pullup ->> pre-config pullups disabled have the option to mount external pull-up or pulldown?
TCK,TDI,TDO,TMS
PWRDWN_B leave open
DXN DXP connect to sense lines
VBATT, RSVD, do not connect
VCCAUX 3.3V to be well decoupled, partial layer
configuration signals (all dedicated and dual-use lines) mixed 2.5V/3.3V go to Sum processor
Jtag signals separate symbol? DXN,DXP?
25 JMM lines 2.5V, no clock lines
all other 2.5V to Sum, including clock lines
3.3V : keep global clock lines separate
all non-clock non-config 3.3V signals can go to single symbol. Not yet known how many lines used for what purpose. Please note that a few differential pairs might be used.
1.5V: no clock lines to be used on input daughter port. and backplane port. all clock lines go along with the remaining I/O to the Sum Processor.