Documentation
on the jet firmware is found at:
http://siplx04.physto.se/~attila/ATLAS/JEM/JET_FPGA_JEM-1.0/Docs/Version_20040820b/
The
documentation consists of
* the specifications document JEMspec10
* schematics, layouts in Gerber format and additional
information in “PCB_design_material.link”
* links to related documents, including documentation on
modules to which the JEM interfaces.
The
specifications relate to the JEM1.1 currently under review and the daughter
modules to be mounted on JEM1.1.
Main
board schematics are made available for both JEM1.1 and the previous version
1.0, so as to document the small number of changes made.
The
production version daughter modules are not yet fully documented:
For the
input modules, please consult the Input v1.0 schematics. V1.1 modifications are
minimal and consist of a local SMBus device for
environmental monitoring only. +5V supply has been made available on JEM1.1,
but this supply is not being used on Input1.1. For modifications of the pin-out
see the .pdf file.
The
G-link board (RM) might be slightly modified to use different buffer types.
Also, if successfully tested, the TLK1201A-based RM might go into volume production
instead.
There
doesn’t yet exist a drawing of the control module (CM). This module will carry
CAN, VME, and configuration related circuitry (TCK buffers only). CAN and VME
will be very similar to the circuitry used on JEM1.0 main board (see JEM1_0_Sheets.pdf,
sheets 2 (CPLD only) and 11).
In case
you are interested in the FPGA design details: The FPGAs
are fully synchronous to a single bunch clock (jet FPGA to 2 clocks). Summaries
of the input and sum FPGA implementation (ISE7.1) including resource use and
maximum clock frequency are available at http://www.staff.uni-mainz.de/uschaefe/browsable/_VHDL_Projects/Report_Files/
(one .html file per FPGA)
Further
documentation can be made available on request.
If you feel there is an urgent need
for clarification on certain issues, please do not hesitate to send me an
e-mail right away -- Uli