Even though the missing energy path is the speed critical one, the energy paths have been pipelined such that the latency is identical for the missing and total energy data. The JEM latency has been measured with the help of an oscilloscope. A data pattern with basically all-0 plus a single non-zero data word was cycled through the JEM. The TTCrx clock deskew was used to vary the phase of the incoming data wrt the JEM global clock (delay scan). Dependent on the clock phase a maximum latency of up to 235ns was measured, if the time is referenced as shown in the screen shot: from the first bit entering the LVDS de-serialiser chip to the centre of the merger signal as measured on the backplane connector. If the backplane signal is referenced at the rising edge, the latency figure is 222ns (8.9 ticks). The measured data are consistent with simulation results.
On JEM1, a minor reduction of propagation delay in the energy sum RTDP might be possible due to the use of faster FPGAs. This might, however, just be enough to compensate for possibly increased delays due to a modified FCAL re-mapping (this part of the algorithm is currently not implemented in its final form). Even if there were an overall reduction in propagation delay possible, this would not necessarily translate into a latency reduction, since we are operating a single-clock synchronous pipelined system in which most pipeline stages are constrained (input flip-flops, registered LUTs (Xilinx blockram), and output flip-flops). Even though a multi-phase clock regime is possible due to Virtex-2 DCMs, this is not currently under consideration. Half a clock tick can probably be gained in using the DDR registers on the Virtex-2 I/O pads for multiplexing / de-multiplexing rather than CLB-based circuitry.
The delay introduced by the phase adjustment circuitry, as shown in the delay scan diagram could be avoided, if the global JEP TTC-clock were phase aligned so that the latest arrival of any data word on any of the LVDS channels were in phase with the global clock. This will require a delay scan with an overall latency optimisation throughout the L1Calo system. While the firmware-based decision logic for the phase detection and adjustment was shown to work on JEM0, a purely software-based delay-scan scheme would certainly have its advantages.