Even though the missing energy path is the speed critical one, the energy paths have been pipelined such that the latency is identical for the missing and total energy data. The JEM latency has been measured with the help of an oscilloscope. A data pattern with all-0 plus a single non-zero data word was cycled through the JEM. The screen shot (see vertical cursors) shows a total latency of 200ns from the serial data on the LVDS link cable (ie. on the input pins of the de-serialisers) to the backplane JMM lines. The input data (blue, channel 2) are referenced at the end of the data word (last data bit arrived). The output data (yellow, channel 1) are referenced at the centre of the 25-ns data window. The screen shot was taken with any additional delay and phase correction set to zero. For incoming data with arbitrary phase relationship the automatic phase adjustment circuitry might add up to a full tick of latency to even the latest incoming data, if it decides in favour of a phase shifted sampling point. The decision logic is sensitive to signal integrity only. It is not latency aware.
The measured data are consistent with simulation results.
On JEM1, a minor reduction of propagation delay in the energy sum RTDP might be possible due to the use of faster FPGAs. This might, however, just be enough to compensate for possibly increased delays due to a modified FCAL re-mapping (this part of the algorithm is currently not implemented in its final form). Even if there were an overall reduction in propagation delay possible, this would not necessarily translate into a latency reduction, since we are operating a single-clock synchronous pipelined system in which most pipeline stages are constrained (input flip-flops, registered LUTs (Xilinx blockram), and output flip-flops). Even though a multi-phase clock regime is possible due to Virtex-2 DCMs, this is not currently under consideration.
The delay introduced by the phase adjustment circuitry could be avoided, if the global JEP TTC-clock were phase aligned so that the latest arrival of any data word on any of the LVDS channels were in phase with the global clock. This will require a delay scan with an overall latency optimisation throughout the L1Calo system. While the firmware-based decision logic for the phase detection and adjustment was shown to work on JEM0, a purely software-based delay-scan scheme would certainly have its advantages.