While the optimum sampling phase of the de-serialised 40Mb/s input data is determined on both the CP and the JEP automatically by firmware on a per-channel base, any adjustment in terms of full ticks will have to be done after each phase adjustment under software control. This global adjustment operation will involve reading out and comparing all input channels of the full JEP (CP). So as to avoid the need for separate phase-adjust and latency-adjust cycles, in the following a mechanism using a common data pattern for both types of adjustment will be discussed. While this mechanism is initially tuned to the requirements of the JEP, a common JEP / CP synchronisation scheme should be devised eventually.
The data source (DSS or PPr playback) memory will be filled with a repetitive pattern:
0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x13, ...
Please note that this pattern is odd parity encoded with the parity bit the lsb (bit0). The next significant bit (bit1) is alternating 0/1/0/1... and is used for phase determination. Bit 4 is set to one for a single bunch tick every 8 clock cycles only and allows for the coarse delay correction. In the current JEM firmware up to 3 ticks of correction are possible under VME control.
The synchronisation mechanism assumes that all TTC-driven JEM clocks are already tuned to their final values. Whenever for reasons of system time-in adjustments are made to one or several TTC clocks, it will be necessary to repeat the input synchronisation cycle.
The control software will have to upload the synchronisation pattern to the DSS (or PPr) and cycle the data in an infinite loop. All data sources need to be started synchronously via a broadcast command. In the initial step the optimum sampling phase is determined individually for each data channel. This action is started by a TTC broadcast command. However, since the process does not require knowledge of relative timing of individual modules, a VME command can be used to start up the algorithm, too. Once the optimum sampling phase is determined, the control software should read back the phase settings from the VME registers and transfer them into the data base, from where they can be loaded after system re-start. In the second step the JEM starts spying on the inputs of the Input Processors and records the data. It is vital that all data sources and sinks are started synchronously by a TTC command, since the timing inter-calibration of individual modules is to be determined in this step.
The spy memory contents are read back into the VME crate-CPUs and the patterns are compared. It is sufficient to read out the first 8 ticks worth of data, since the pattern is repetitive. The analysis of these data will involve non-local data processing in the final setup, since two JEP or four CP crates are to be brought in phase. The software has to determine the channel with latest arrival time. Once this is found, the required delay for each channel is determined. The '1' appearing in bit 4 of the input data word acts as a marker. All channels are adjusted. One might wish to read out the spy memories with a fresh set of input data to confirm that all channels are in phase now. The maximum correction required will be two bunch ticks or less.
The coarse delay adjustment will have to be repeated whenever the phase is re-adjusted, since even with constant cable delays and device skews the phase determination algorithm might choose a different sampling phase next time it is run, due to jitter.
Please note that at current no spy memories are available on the JEM Input Processors. In a first stage a single bit of spy memory per input channel will be introduced, so as to capture the marker bit.. On JEM1 the full input path will be spyable.