Goal: to test full JEM functionality except CAN access and flash-memory configuration. Test all external interfaces.
JEM0.1 standalone tests almost completed: energy sum RTDP from serial LVDS data, to merger port (on-FPGA), playback, spy (on energy sum merger lines), FIO basic tests. Slice data captured on the ROC FPGA outputs. Also tested: global clock distribution incl. TTC interface basic tests. Input synchronisation scheme has just been improved and requires further tests. The final jet algorithm needs to be merged with the energy sum code before tests on the jet data path (including full FIO tests) can begin. ROI interface to be implemented and tested (skeleton available). G-Link interfaces to be improved (EP89 and optimisation of some resistor values).
JEM0.2 almost fully tested. Long-term tests required.
Online software: production under way. HDMC and module services partially existent. Interface to test vectors and upload software currently being written . Missing: software for determination of the latency correction on the input signals. The UK-written TTC control software will have to be modified and also the data bases need to be modified since the JEMs use TTC daughters which cannot be configured externally. The software needs to look up the TTCrx IDs of the JEMs in the data base and send addressed commands to set the programmable delays.
Even though all above tests have been performed with existent software, systematic tests for low-level errors might require additional work on the software. Please note that the software used to perform the tests described above was not developed in the Atlas online software framework and can not be run at RAL. Due to limitations on the effort available not all required software modules will be available right from the beginning (Thomas: software list please: what do we want to test in detail, what additional software is required)
Simulation: Sets of test vectors to stimulate the real-time data path, along with expected results, are available. At current the simulation is not integrated in the SJH framework.
Test vectors are loaded into playback memories and results are captured on spy memories. Playback and spy may be located on the same module, or on different modules, for test of the interfaces. The captured results are compared to the expected results, as obtained from a simulation. The expected results are stored in the test vector files, along with the stimulus.
The following hardware will be required for full tests of all interfaces. (->spread sheet)
For initial standalone tests the JEM(s) should be run on the bench with local clock, VME cable and an external 5V/10A power supply (RAL!). The two JEMs can be clocked directly from the TTCvx with help of adapter cables, independent of the TCM clock distribution. DSSs might be used for initial tests on the ROD interface.
Access to Xilinx development tools when at RAL:
1) Xilinx / Mentor software: remotely accessible on
debussy.physik.uni-mainz.de . Access should be made available to Stockholm
design environment, too. Configuration files will be uploaded to the local VME
systems with scp.
2) In the event of a failure of (or update to) the VME CPLD, access might be
required to a local PC with parallel port, Xilinx X-checker (parallel) cable and Xilinx ISE
or Webpack software for re-configuration of the VME CPLD.
1. Set up TTC system (TTCvi,TTCvx,TCM) No software required 2. Repeat standalone tests JEM0.1 3. Repeat standalone tests JEM0.2 software existing: - Load and configure FPGAs - Read playback memory - Write Spy memory - Check Link status, parity errors - Read test vectors To do: Read sequence of test vectors Test the testvectorreader program Comparing input and output 4. Test the jet code (playback,spy) in core region no software from Mainz 5. Fully integrate DSS and JEMs in the TTC environment To do: Define format, write a DSS reader, identify the channels 6. Run the input synchronisation software and adjust the input signal latency According to Ulis description write a simple algorithm (see http://www.uni-mainz.de/~uschaefe/browsable/JEMdocs/RAL-tests/insync.htm ) 7. Run a delay scan to determine the optimum sampling phase of the FIO inputs Simple software to do a delay scan List of attendance: Cano 20.-24.1 Uli 20.-24.1 Attila 20.-24.1(?) Thomas 20.-24.1 Exact travel dates will be finalised on Monday 13th of January.