Test Results, Status and Work Plan Jan. 25 2003

Test status:

Both JEM 0.1 and 0.2 have been successfully operated in a crate environment at RAL. The  JEMs were clocked by the TTC system. The RTDPs of the JEMs have been exercised by both internal data from the playback memories and LVDS data sent by a DSS on 16 channels. Hardware and firmware were tested to the extent permitted by the software, which was mainly written on the spot.

Transmission tests using playback memories:
The data transmission from playback to spy memories was successfully tested for the energy sum path (ET only). No systematic tests of all channels / both modules yet. No jet path tests yet.

Transmission tests using DSS:
All tested channels lock to the LVDS signals. The channels stay in lock with pseudo random numbers. Constant data were sent from the DSS and the results appeared correctly on the energy trigger outputs. No systematic tests of all channels / both modules yet.

Software status:
Software is ready to fill playback memories, start playback and spy memory operation for 256 ticks and read out spy data. Also available is software to spy on energy results obtained from the LVDS - received data. The DSS TV-reader is almost finished.

Work to be done:

Hardware/Firmware:
Add TTC lock monitor and TTC reset to the TTC daughter / control FPGA circuitry to allow for software controlled reset. Modifications of the TTCrx clock buffer scheme might be required, depending on timing test results. Clock monitor circuitry should be added on the control FPGA, if possible, so as to rule out that despite TTC 'ready' signal one of the required clocks does not come up. The issue of unreliable read operations on the VME CPLD will have to be tackled. Attila will need to supply working configurations for both the trigger algorithms and the FIO path readout.

Software:
In preparation of the next test session, scheduled for the end of February, the software will have to be expanded considerably, so as to allow for systematic tests of all channels of both modules, the operation of the input synchronisation (incl. delay settings), and the delay scan of the FIO data transmission. Since a Mainz visit by Attila is scheduled from Feb. 10, all jet and TTC related work should preferably take place in that period. Some discussion will be needed on the required error limits, and whether they can be achieved under software control, or if dedicated firmware is required (PRN generator / checker).

  1. make sure the existent energy path playback / spy software is suitable to automatically process large amounts of test vectors  in a batch operation to allow for error tests down to lowest levels for all channels / both modules (might require some work from Murrough).
  2. expand the software to handle jet data from two modules (Attila/Sam). Common test vector files to verify both the jet and sum paths in one go will probably  be required at a later stage only.
  3. modify the playback / spy software so as to make it suitable for the readout of the debug configuration of the main processor (Attila/Sam).
  4. write software for input synchronisation
  5. include software  for TTCrx reset / global reset on DSS and JEMs
  6. Write TTCvi control based on existent code from RAL /B'ham. (Attila/Sam)
  7. Finish DSS  playback software (Bruce).
  8. write software for FIO delay scan (Attila/Sam)

Intense discussions with RAL/B'ham are probably required to sort out the issue of process synchronisation for modules living in different crates. As a quick fix it might be possible to run the software independently on each of the crates and proceed a pointer in a list of operations with help of TTC broadcast commands.

 

Tests at Mainz:

  1. verify error free operation on all energy paths / all channels / both modules via playback / spy
  2. repeat measurements with DSS as a data source
  3. test input synchronisation including automatic delay control (might require delay scan / cable length variation operation of both LVDS daughters on different TTC clocks) (done , 14.2.2003)
  4. test and adjust internal timing (clock to parallel data) of JEM TTCrx daughter done, --> use falling edge clock on control FPGA TTC data inputs!
  5. test the jet code (playback,spy) in core region (A) (S/W required)
  6. run a delay scan of the FIO inputs (loopback adapter) and record optimum delay setting (A) (use debug config)
  7. determine FIO BERs with loopback adapter (A)(debug)
  8. generate LVL1Accept via TTC and spy on results in ROC (slice, [ROC update required for ROI readout]
  9. operate JEM control via TTC (spy, sync) (requires work listed in 4.)

Further tests:

At RAL, most likely from Feb 24, further tests will take place (next UK meeting Feb.27th? B'ham?).

  1. FIO tests using real backplane
  2. ROD and CMM related tests (Andrea)