Test Plan Birmingham August, 2006

* time in all interfaces

- all CLKDES1 via scope / HDMC / data base (1)

- operate LVDS inputs at fixed global offset from (1), all input channels forced to 0 phase, 0 delay

- FIOs via delay scan (binary counter pattern)

- CMMs via CMM tool (R. Booth?)

* confirm proper operation of all interfaces of the supposedly working modules (1*JEM1.2, 3* JEM1.3)

- LVDS via ramp of length 512 (possibly done already)

- DAQ G-link via gLinkTest

- ROI G-link via gLinkTest and special jet firmware (optional)

- FIOs and CMMs are done already...

* time in DAQ and ROI(?) chain

operate full system with readout. check for errors on DAQ.

Make sure we can check for errors on all interfaces with maximum traffic throughout the system.

worst case patterns :

LVDS alternating bits

LVDS data generating maximum concurrent switching on FIOs

ramp pattern on FOIs

patterns on Glinks?

Patterns on merger lines