-- hds header_start
--
-- VHDL Architecture INP_FPGA_sync.syncro.syncro
--
-- Created:
--          by - schlt014.UNKNOWN (IPHCIP12)
--          at - 15:17:45 08/28/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library unisim;
use unisim.all;


ENTITY syncro IS
	port(
		CLKin		:	in std_logic;
--		CLK80		:	in std_logic;
		Inp			:	in std_logic; 
		phase			:	in std_logic;
		oup		: out std_logic
		);
END syncro ;

-- hds interface_end
ARCHITECTURE syncro OF syncro IS
--signal declarations

component CLKDLL
      port (CLKIN, CLKFB, RST : in STD_LOGIC;
      CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;

component BUFG 
  port (
  	I   : in std_logic;
        O    : out std_logic
	); 
end component;
--
component IBUFG 
  port (
  	I   : in std_logic;
        O    : out std_logic
	); 
end component;

--signal phase : std_logic;
signal gnd,clk80,clk80a,clk40,clk40a,ce,clk_in : std_logic;
BEGIN
-------------------------------------------------------------
--phase detection  bit 0
-------------------------------------------------------------
GND <='0';

dll2x  : CLKDLL port map (CLKIN=>CLK_IN,   CLKFB=>CLK80, RST=>GND,
                          CLK0=>CLK40a,   CLK90=>open, CLK180=>open, CLK270=>open,
                          CLK2X=>CLK80a, CLKDV=>open, LOCKED=>open);

-- BUFG Instantiation
BUFG_40: BUFG
  port map (
  	    I => CLK40a,
            O => CLK40
  	   );

BUFG_80: BUFG
  port map (
  	    I => CLK80a,
            O => CLK80
  	   );


U0_IBUFG: IBUFG
  port map (
  	    I => CLKIN,
            O => CLK_IN
  	   );


ce <='1' when phase=clk40 else '0';
process (CLK80)
begin
   if CLK80'event and CLK80='1' then  --CLK rising edge
      if ce='1' then		oup<=inp; end if;
   end if;
end process;



END syncro;