29.04.2014 08:44:23

Phase-1 compatible links to backplane, according to Dave Sankey scheme. That’s 2*8 pairs from the backplane (fabric interface). Mezzanine. Clock, TTC data, ROD links. Since in this case the ROD is external, the links should come from processor FPGAs. Caution! That would require additional clocks that we haven’t thought about and might not be possible! But in this case a separate FPGA might have to sit on the mezzanine as well!

Check Ethernet backplane link. Base interface. Future use of something different from 1G Ethernet would be possible only if running onto mezzanine

We discussed widening phase0 ROD/control path by using MGTs out of processors. Same argument as above, due to limitations on clocks that might be possible running at 40.08 multiple only. What is the current MGT budget on the Kintex device?

Not to forget: Kintex clocking

We are probably free to decide where the scsi connector goes but we need to inform CTP on consequences:

Fixed routing 16+18 or 17+17, also remind them that the source is 2 FPGAs and that has consequences on clock and parity!