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30.05.2012 15:28 update drawings of clock and control circuitry in sect. 3
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An initial version of the L1Calo specifications
is now available at:
http://www.staff.uni-mainz.de/uschaefe/browsable/L1Calo/Topo/
Documentation is generally made available as .docx and .pdf.
Detailed design documentation (schematics, layout, and drawings) will be made available at:
http://www.staff.uni-mainz.de/baussh/TOPO/
Work on the documents will be continued over
the next weeks...
Please let us know if you find any vital information missing. We will certainly
try and add further documentation. We are suffering a bit from the fact that no
complete requirements document is available, signed off by prospective “users”.
Exact predictions of input bandwidth and processing power needs are difficult.
An attempt was made earlier to write up a few lines on requirements. The
document is found in the same folder ( http://www.staff.uni-mainz.de/uschaefe/browsable/L1Calo/Topo/topoURD.docx)
Lacking some
requirement details, the main reason to build L1Topo as described is
that we need, for latency reason, to put as much input bandwidth and processing
power into L1Topo as possible with exactly two processor FPGAs. The main reason
to go for exactly two FPGAs is the fact that only for this scheme we are able to
maximise chip-to-chip bandwidth, while keeping latency on the chip-to-chip
boundary as low as possible, using standard parallel FPGA connectivity.
The links to documentation on related projects are outdated and incomplete.
Please point us at documentation of your interfacing systems to allow us
include the links in section 1.
There are definitely open questions about ATCA compliance for two reasons: It’s
not yet decided whether full compliance is required, and ATCA specifications
are not available to the module designers, but the community might be able to
supply with their favourite Zone-2 pin-out.
Early comments are particularly welcome to allow us improve documentation
before June 12.