Topo processor FPGA configuration

The topo processor will be equipped with two processor FPGAs and a control FPGA. The processors will require about 230 Mbit of configuration data each (XC7VX690T). The control FPGA (XC7K) will be configured with less than 100Mbit.

The FPGAs will be configurable through several paths.

All processors will be joined to a single JTAG boundary scan chain. This chain does not contain any non-FPGA devices. The three FPGAs can be configured via USB/JTAG adapter, when operated on the bench. There are several non-volatile configuration storage options available on the topo processor.

1) The JTAG chain can be wired to a System ACE configurator, consisting of System ACE chip, CF card, and crystal clock. The System ACE chip will be wired for correct power-up operation via a small CPLD or via wire straps. The programming port of the System ACE chip will be wired to the control FPGA.

2) The control FPGA will be wired to an SPI memory (SO-16 package). The control FPGA is meant to carry non-algorithmic code only. Occasional firmware updates can be performed via JTAG access / IMPACT tool. Since multi-boot operation is supported, only an initial “golden” configuration needs to be programmed via JTAG, subsequent upgrades can be done remotely. Specific firmware/software might have to be developed before in-situ updates are possible.

3) The processor FPGA configuration will need to be updated, whenever a change of algorithms is required. Configuration selection and modification is controlled by the fixed-function control FPGA. The control FPGA is accessible via Ethernet, whenever the module is powered up. The control FPGA will load a default configuration from a suitable local non-volatile high-capacity storage device. Alternative configurations can be directly uploaded from the module controller, connected via Ethernet. The non-volatile storage can be updated via the Ethernet as well. For reason of configuration speed the non-volatile device is currently assumed to be a CFI parallel NOR flash device. Alternatively a SD card might be considered.

Parallel NOR flash will allow for high configuration speed (read throughput ~0.5Gb/s) but is slow to program (~minute per typical configuration data volume of a single FPGA). NAND flash (SD card) has lower read and considerably higher write rates than NOR devices.

Initially SPI single boot configuration will be used for the control FPGA, since this approach will require neither firmware nor software development. Without any prior firmware development, the processor FPGAs will be configurable via JTAG / System ACE only.

The topo processor might contain small CPLD devices for purpose of static module control. These devices would be wired to a separate JTAG chain. They wouldn’t need to be reconfigured after module commissioning. Front panel access is not required for this chain.