jFEX details / check list
30/03/2015 15:38:31
There is
some duplication below, partially intended…
Open questions,
notes
·
Are
swap rules fixed now? Per bank…?
·
Are
differential polarity swap rules fixed?
·
·
Micro-
versus MiniPOD
·
Floorplan
·
Cooling
channels!
·
Routing
channels
·
Mainboard
limited to 1 slot width à fibre routing through-mPOD
·
Hardware
Address to which locations? Extension module, configurator, merger?
·
Any
other Zone 1 issues?
·
differential
bus from extension module to 5 FPGAs to contain one clock capable pair each
·
HR
pins unused except possibly a few lines from mezzanine, reserved for input into
merger
·
All
I/O 1.8V
·
DCI
enabled for single ended lines (VRP). PCB impedance control for single ended lines???
·
All
single ended configuration/JTAG links source terminated with discrete resistor
·
JTAG
point-to-point versus daisy chain (speed!)
·
Design
for permanent JTAG access (chipscope/ILA)
·
Outgoing
links from processors and merger require LHC clock multiples à separate tree(s) required
·
How
do we get (subset of) LHC data to *all* processors?
·
I2C
/ SPI via USB boxes
·
A
small number of Finisar transceivers?
·
IPMC
Ethernet to front panel and/or 2nd hub?
·
Do
we have the “use of backplane” document?
·
Improvements
on IPMC firmware update / reset (Adam) jumper or FET for power supply
·
Anything
to do wrt FPGA analog
interface? On Topo it has basically been disabled…
Allocation to
mainboard
·
standalone
capability
·
JTAG
·
5
FPGAs
·
All
MPODs
·
Power
·
IPMC
/ sensors / hardware address
·
Auxiliary
sensors to mezzanine
·
Clock
trees
·
Local
crystals
·
Possibly
1 Ethernet phy, 1 jitter cleaner????
Allocation to
daughter(s)
·
Configuration
·
Front
panel (LEDs, connectors, make list!)
·
Clock
generation / cleaning
·
Final
module control
·
I2C
engine (microcontroller?)
·
I2C
to USB
Module control
·
Extension
mezzanine
·
Merger
Clocking/LHC
data
·
Repeater
on backplane? Signal level monitoring?
·
Trees
on mainboard, LVDS DC coupled
·
Local
crystals
·
LHC
data might be required on all FPGAs
MGT
clocking
·
Conditioning
on mezzanine?
·
Trees
on mainboard, CML AC coupled (check voltage swing requirements)
·
Input
tree: 3 local crystals/ 1 LHC clock
·
LHC
derived output clocks?
·
125MHz
crystal clock for IPbus
·
Any
other ?
Operational
modes
·
Standalone
(initial and fall-back)
·
local
crystal mainboard
·
Test
route for LHC data???
·
Ethernet
front panel
·
DAQ
out probably not accessible? DAQ links need to go straight out for BER reason
·
Configuration:
JTAG only
·
Mode
setting via resistor straps
·
System
·
all
clock/control/LHC/DAQ from backplane, all duplicate paths (two hubs)
·
All
via extension mezzanine???? Just the duplicates?
·
LHC
clock
·
LHC
data
·
Ethernet
(2*as well!)
·
DAQ
·
Override
mode settings from mezzanine
Mainboard
components list
·
Backplane
connectors el. /opt.
·
Primary
and secondary regulators
·
5
FPGAs
·
MPODs
·
Local
crystals
·
Clock
trees CML and LVDS including MUXes
·
Resistor
straps for MUXes and FPGA configuration modes
·
JTAG
drivers
·
JTAG
level converters, if required
·
Sensor
devices for IPMC
·
Sensor
devices for IPbus
·
·
IPMC,
handle, ATCA LEDs
·
Extension
mezzanine
·
Front
panel mezzanine
·
Separate
configuration mezzanine
Front panel
LEDs (error red, ok green, activity blue?)
·
Power
LEDs
·
Done
LEDs
·
Error
LEDs
·
IPbus activity?
·
L1A
·
Broadcast?
·
Front panel
connectors
·
JTAG
header or USB
·
SPI/I2C
headers on front panel????
·
Clocks
MMCX?
Other front
panel functionality
·
Flash
card
·
Handle
switch
Old notes, partially irrelevant now
·
·
Scheme for config banks, analog circuitry
·
Configurator:
mezzanine ? Artix ? Zynq ?
·
Power rails:
current estimates
·
What device
for static configurations: Artix/Zynq
vs. CPLD, wire straps for options required early on ?
·
Tightly
vs. loosely coupled diff pairs : Differential 100R vs. 50||50
·
Any
board level initialization needs to be specified to 1)logic
level, 2) when (power up, fast programmable device, post FPGA configuration,…)