jFEX details / check list

15/04/2015 10:24:36

 

 

There is some duplication below, partially intended…

 

A)      Open questions, notes

 

 

1.       Recently discussed: PMA loopback most likely not possible with crystal reference, clock resource requirement for TXOUTCLK to be checked.

2.       Need to derive new local test strategy: due to loopback issue any local tests will be possible only if MGT refclock and global clock coming from same sourceà divide down xtal clock in FPGA, route out to local GCK tree and to external source/sink modules.

3.       Alternatively use jitter cleaner from day 0

4.        

5.       Are swap rules fixed now? Per bank…? Always connect full banks to one another, swap within banks

6.       What level of swapping is allowed for incoming / duplicated MGT links?

7.       Are differential polarity swap rules fixed? Polarity swap allowed for MGTs, not for LVDS

8.       All processors routed symmetrically/identically to allow for same configuration in all 4 ?

 

9.       Bottom component height depends on various parameters. What limit do we settle for?

10.     

11.    Micro- versus MiniPOD

12.    Floorplan

13.    Cooling channels!

14.    Routing channels

15.    Mainboard limited to 1 slot width à fibre routing through-mPOD

 

16.    Hardware Address to which locations? Extension module, configurator, merger?

17.    Any other Zone 1 issues?

18.    differential bus from extension module to 5 FPGAs to contain one clock capable pair each

19.    probably most merger lines single ended to allow for David’s IPbus slave scheme

20.    HR pins unused except possibly a few lines from mezzanine, reserved for input into merger

21.    All I/O 1.8V

22.    DCI enabled for single ended lines (VRP). PCB impedance control for single ended lines???

23.    All single ended configuration/JTAG links source terminated with discrete resistor

24.    JTAG point-to-point versus daisy chain (speed!)

25.    Design for permanent JTAG access (chipscope/ILA)

26.    Outgoing links from processors and merger require LHC clock multiples à separate tree(s) required

27.    How do we get (subset of) LHC data to *all* processors?

28.    I2C / SPI via USB boxes

29.    A small number of Finisar transceivers?

30.    IPMC Ethernet to front panel and/or 2nd hub? Via mezzanine? Magnetics?

31.    Do we have the “use of backplane” document?

32.    Improvements on IPMC firmware update / reset (Adam) jumper or FET for power supply

33.    Anything to do wrt FPGA analog interface? On Topo it has basically been disabled…

 

 

 

 

 

B)       Allocation to mainboard

1.       standalone capability

2.       JTAG

3.       5 FPGAs

4.       All MPODs

5.       Power

6.       IPMC / sensors / hardware address

7.       Auxiliary sensors to mezzanine

8.       Clock trees

9.       Local crystals

10.    Possibly 1 Ethernet phy, 1 jitter cleaner (probably required due to PMA loopback Xtal ref issue

 

C)       Allocation to daughter(s)

 

1.       Configuration

2.       Front panel (LEDs, connectors, make list!)

3.       Clock generation / cleaning

4.       Final module control

5.       I2C engine (microcontroller?) (note that i2c/SPI required early on for jitter cleaner)

6.       I2C to USB

 

D)      Module control

1.       Extension mezzanine

2.       Merger

 

E)       Clocking/LHC data

1.       Repeater/MUX on backplane?  Signal level monitoring?

2.       Trees on mainboard, LVDS DC coupled

3.       Local crystals

4.       LHC data might be required on all FPGAs

 

F)       MGT clocking

1.       Conditioning on mainboard/mezzanine?

2.       Trees on mainboard, CML AC coupled (check voltage swing requirements)

3.       Input tree: 3 local crystals/ 1 LHC clock XXX note change of scheme

4.       Input tree: Mux local jitter cleaner/mezzanine

5.       LHC derived output clocks?

6.       125MHz crystal clock for IPbus

7.       Any other ?

 

 

G)      Operational modes

 

Standalone (initial and fall-back)

 

1.       local crystal mainboard XXX note change of scheme

2.       Test route for LHC data???

3.       Ethernet front panel

4.       DAQ out probably not accessible? DAQ links need to go straight out for BER reason

5.       Configuration: JTAG only

6.       Mode setting via resistor straps

 

System

 

7.       all clock/control/LHC/DAQ from backplane, all duplicate paths (two hubs)

8.       All via extension mezzanine???? Just the duplicates?

9.       LHC clock

10.    LHC data

11.    Ethernet (2*as well!)

12.    DAQ

13.    Override mode settings from mezzanine

 

 

 

H)      Mainboard components list

1.       Backplane connectors el. /opt.

2.       Primary and secondary regulators

3.       5 FPGAs

4.       MPODs

5.       Local crystals

6.       Clock trees CML and LVDS including MUXes

7.       Resistor straps for MUXes and FPGA configuration modes

8.       JTAG drivers

9.       JTAG level converters, if required

10.    Sensor devices for IPMC

11.    Sensor devices for IPbus

12.     

13.    IPMC, handle, ATCA LEDs

14.    Extension mezzanine

15.    Front panel mezzanine

16.    Separate configuration mezzanine

 

I)         Front panel LEDs (error red, ok green, activity blue?)

1.       Power LEDs

2.       Done LEDs

3.       Error LEDs

4.       IPbus activity?

5.       L1A

6.       Broadcast?

·          

 

J)        Front panel connectors

 

1.       JTAG header or USB

2.       SPI/I2C headers on front panel????

3.       Clocks MMCX?

 

K)       Other front panel functionality

·         Flash card

·         Handle switch

 

 

L)       rear

 

Zone 1

·         As Topo

 

Zone 2

·         Fabric channels all AC coupled

·         Base channels with magnetics (what type?)

 

Zone 3

·         Quite like Topo, see eFEX PCB mod. Final?

 

M)     Interfaces external

1.       Nnn Incoming MGT links, default crystal reference, optional LHC clock

2.       2*6 Backplane outgoing MGT links, LHC synchronous, multiple X

3.       2* Incoming clean backplane clock

4.       2* incoming LHC data MGT link, reference maybe crystal???? Or clean clock *1 ????? 

5.       Mm Topo links from merger, synchronous multiple Y

6.       Kk Topo links from each processor, synchronous multiple Y

7.       Ethernet from two hubs. 1x SGMII (ref. 125MHz), 1x into IPMC????

 

N)      Interfaces internal

1.       Processor/merger links, LHC clock, might possibly be same clock as incoming links, however in this case required to be LHC, not Xtal!!!!!

2.       Secondary IPbus links, 125 MHz reference. If we want to run the links synchronous, it will have to be a common 125MHz tree!

 

 

 

O)      Questions regarding backplane use

 

1.       Is the backplane clock guaranteed with automatic failover? Yes ! see review report

2.       Are other people using repeater on backplane?

3.       Is 2nd hub assumed to connect to IPMC Ethernet ?

 

 

P)       Parts list

·         Magnetics Würth 749020111 Digikey 16.64 mm x 8.99 mm x 2.29 mm. – no, use the one on L1Topo

 

 

 

 

Old notes, partially irrelevant now

 

·          

·         Scheme for config banks, analog circuitry

·         Configurator: mezzanine ? Artix ? Zynq ?

·         Power rails: current estimates

·         What device for static configurations: Artix/Zynq vs. CPLD, wire straps for options required early on ?

·         Tightly vs. loosely coupled diff pairs : Differential 100R vs. 50||50

·         Any board level initialization needs to be specified to 1)logic level, 2) when (power up, fast programmable device, post FPGA configuration,…)