jFEX details / check list

05/09/2014 08:39:37

· lead time engineering samples XCVU160 vs. XCVU190 FLGC2377

· allocate IO banks: specific pins / general IO, banks pin swappable

· parallel diff observe polarity ? Local inversion? New serdes resources require correct polarity ?

· MGT links polarity, local inversion

· Scheme for config banks, analog circuitry

· Configurator: mezzanine ? Artix ? Zynq ?

· Power rails: current estimates

· Define 5^th FPGA

· What device for static configurations: Artix/Zynq vs. CPLD, wire straps for options required early on ?

· Any single ended connectivity with controlled impedance?

· Source damping resistors required on which lines ? All? Clocks !!!

· Tightly vs. loosely coupled diff pairs : Differential 100R vs. 50||50

· Global clocks directly from backplane ?

· MGT clocks jitter cleaner (jitter requirements on UltraScale)?

· Block diagram clock trees. How many ?

· Clock signal levels, AC vs. DC

· Ultrascale internal MGT clock routing vs. signal integrity.

· Any board level initialization needs to be specified to 1)logic level, 2) when (power up, fast programmable device, post FPGA configuration,…)

· Mini vs. MicroPOD ?????????