Questions and issues are collected here before being pasted to the slides. Formatting will take a few moments and I am a bit late...

This list will grow until Tuesday !


Power:
large FPGAs can easily dissipate 30 Watt. Current standard ATCA power modules (ATC250) rated 250W. might require different (larger?) component
High-power crates can today supply and cool up to 450W/slot 

Increase in dissipation for larger jet environment

Can we specify a default jet algorithm ?

with current baseline data from each FPGA in the system (48) could be routed into L1Topo on individual fibre. Is that ok or should we allow for board level merging at the expense of higher latency ?