Uli starts with a summary of the JEP status: 
Currently two JEMs are up and running, JEM0.1 considered a fully functional prototype ready 
to go into sub slice test. A 3rd  module, JEM0.2 is under production. It carries a main 
processor of increased logic capacity. The firmware is nearly complete and tested, on-line 
software is available, though largely not yet converted into the module services framework.
Work on the real-time data path of the energy sum merger starts after the B’ham meeting. 
Documentation has been updated.
So as to get ready for the sub-slice test at RAL, a few further tests are required on the input 
synchronisation circuitry and on the FIO data resynchronisation. The ROI interface has not 
been implemented yet. Since it is a copy of the DAQ interface, no dedicated tests are assumed 
to be necessary. Uli explains requirements and goals for the sub-slice test at RAL. The tests 
will require infrastructure assumed to be available at RAL due to previous and concurrent 
CPM tests. The JEM should be ready to go into the sub-slice test by the end of the month.

Uli explains that due to the trigger-wide move from 1.6mm card rails to 2mm rails the current 
JEM, though otherwise functional, cannot act as a basis for the production modules. A few 
minor bugs will have to be fixed on the production modules and FPGA resources will be 
allocated differently. 

The baseline for a JEM re-design is presented. The detailed design started in September. Uli 
explains problems encountered due to the high density of vias required on de-serialisers and 
FPGAs. The design work is delayed and together with the PCB manufacturer a solution is 
sought. A daughter board construct is seriously considered. 

Further old-style JEMs will be manufactured for the slice test in 2003, to make sure that the 
algorithms can be tested even if the prototype of the production modules is not available in 
time.