Uli starts with a summary of the JEM0 status: 
Three JEMs are up and running, JEM0.1 and JEM0.2 are to module0 specifications except flash ROM and CAN interface. They have been successfully tested at RAL in January.

A block diagram of JEM1 is shown and some problems with the highly complex PCB design are explained and as a solution a daughter module concept is presented. The concept was agreed on during a review at RAL in December, 2002. All modifications required for JEM1 wrt JEM0 are shown. The input daughter module design is shown along with a drawing of the differential connectors to be used. The need for blind or micro vias to provide space for decoupling capacitors is discussed. Finally plans for module production and for the next submodule and slice tests are presented: Input daughter modules will be available at the end of April, the main board will be available in summer 2003. Test boards will be made to allow for input daughter tests before the main board is available. For the time being JEM0s will be used for sub-slice tests.

During the following discussion the possibility of common input modules for both the CP and JEM is raised.