Uli summarises the JEM algorithms and points out some modifications required to allow for transition to the production modules. The energy sum algorithm is partitioned into FPGAs differently and the  Ex/Ey calculation is now performed on jet elements rather than energy sums. Uli explains firmware modifications required to make the code suitable for the Virtex-2 FPGAS and the slightly changed JEM1 architecture. The VME address map changes have some impact on the on-line software. 

In the course of re-writing the VHDL code the coding style was changed to sequential code. Using loops rather than explicit instantiations the code was made compatible to both JEM0 and JEM1. The algorithms are pure VHDL only, no graphical tools were used to avoid dependence on specific implementation tools. Neither Mentor Leonardo nor Xilinx XST do fully satisfy the requirements, but XST was chosen as the slightly more appealing tool. The code was optimised to XST but should be compatible to Leonardo, too.

A block diagram shows the main components of the JEM. JEM1 will be manufactured by Rohde & Schwarz. They are assumed to manage the comlete project from component procurement to assembly. This will be tried out in the prototyping phase to guarantee successful production of the final modules.

Uli reports the current hardware status and the plans for the next months. The number of JEM1s required for the slice test is discussed. Uli tries to assess risks to the production plans and finally summarises some open questions. The issue of opto transmitters is the most urgent one. The final choice must be taken in a couple of weeks time. Some firmware / interface issues (G-link formats, eta/phi mapping and CMM algorithm)can be dealt with at a later stage. 

On behalf of Andrey Uli presents a stand-alone test system for the JEM1 input daughter modules. The software has been tested on JEM0 already, a test adapter will have to be made before the JEM1 daughters can be connected to the test system.