Current plan:

Operate test daughter on ML605 first. Re-use on GOLD. Produce a final daughter module once the required connectivity is known.

Architecture: GOLD carrying 4 daughter connectors and 8 processor FPGAs. Assume two separate daughters carrying each 6SNAPs, unspecified number of fanouts, a CPLD and 2 daughter connectors.

Checklist for test daughter:

SNAP12 receive and transmit (3V3), fanout chips (3V3), CPLD (MUX and level shift 2v5/3V3, Vaux), coupling capacitors immediately after fanouts and before opto transmitters

3.3V from mother, no local regulators (?)

Will carry up to 3*receive, 3 *transmit.

Use GTX receive and transmit pairs as available on ML605 first. Fill up with neighbouring signal pairs.

Specific to ML605:

Provide jitter cleaner module to be plugged into one of the SNAP12 sockets. Based on ICS9FG104D (or ICS844003, or ICS871002I-02, ICS843252(20 to 640)). Externally supplied dirty clock via cable.

Clock recovery in FPGA vs. Ibert limitations à TTCdec ?

SNAP or not SNAP, that is the question. AVAGO ?? will require both 2V5 and 3V3, CML is 2V5!!!

Power: SNAP12 ~2W per receiver ie. 12W per receive daughter. Transmitter 2.4W

Numerology: 2*400 pin connector = 400 signals = 200 pairs

Receive: 36*4 FPGAs=144 pairs.

Transmit: 3FPGAs * 12 pairs= 36 pairs

Total 180 pairs

When using 4-fold fanout, all receivers can be driven, even on test daughter !