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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:19:38 09/18/2024 
-- Design Name: 
-- Module Name:    cpld1_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cpld1_top is
    Port ( 



-- all set to OUT to set pull-high or float. Change that if ever needed...
BOARD_CONF:out std_logic_vector(1 downto 0);
CPLD1_CPLD2:out std_logic_vector(11 downto 0);
CPLDTOCTRLMEZZ:out std_logic_vector(11 downto 0);
U1_CPLD_SPARE:inout std_logic_vector(11 downto 0);
U2_CPLD_SPARE:inout std_logic_vector(11 downto 0);
U1_M:out std_logic_vector(2 downto 0);
U2_M:out std_logic_vector(2 downto 0);
UZ_SPARE_SE:out std_logic_vector(21 downto 12);
PUSH:out std_logic_vector(6 downto 4);
ATCA_HA:out std_logic_vector(7 downto 0);
IPMC_USER:out std_logic_vector(7 downto 0);
IPMC_USER_3V3UP:out std_logic_vector(7 downto 0);
ZONE1_HA:out std_logic_vector(7 downto 0);
SPARE_CPLD1_3V3_UP:out std_logic_vector(9 downto 0);
U1_D:out std_logic_vector(9 downto 0);
U2_D:out std_logic_vector(9 downto 0);
CLK1KHZ_CPLD1:out std_logic;
GCK_SINGLE_CPLD1:out std_logic;
IPMC_UART_RX:out std_logic;
IPMC_UART_TX:out std_logic;
MEZZ_UART_RX:out std_logic;
MEZZ_UART_TX:out std_logic;
U1_CCLK:out std_logic;
U1_CSI_ADV_B:out std_logic;
U1_DONE:out std_logic;
U1_DOUT_CSO_B:out std_logic;
U1_FCS2_B:out std_logic;
U1_INIT_B:out std_logic;
U1_PROGRAM_B:out std_logic;
U1_PUDC_B:out std_logic;
U1_RDWR_FCS:out std_logic;
U2_CCLK:out std_logic;
U2_CSI_ADV_B:out std_logic;
U2_DONE:out std_logic;
U2_DOUT_CSO_B:out std_logic;
U2_FCS2_B:out std_logic;
U2_INIT_B:out std_logic;
U2_PROGRAM_B:out std_logic;
U2_PUDC_B:out std_logic;
U2_RDWR_FCS:out std_logic);

--a:out std_logic :='1');


--			bank1 : in  STD_LOGIC;
--			bank2 : in  STD_LOGIC;	
--			bank3 : in  STD_LOGIC;
--			bank4 : in  STD_LOGIC;
------- dummy inputs to simplify bank voltage assignment
--			a : in  STD_LOGIC;
--          b : in  STD_LOGIC;
--           c : out  STD_LOGIC;
--           d : out  STD_LOGIC);
end cpld1_top;

architecture Behavioral of cpld1_top is

attribute iostandard:string;
--attribute iostandard of CPLDTOCTRLMEZZ : signal is "LVCMOS33";
--attribute iostandard of * : signal is "LVCMOS33";
--attribute PULLUP : string;
--attribute PULLUP of CLK1KHZ_CPLD1 : signal is "NO";
--attributePULLUP of signal_name:signal is "{YES|NO|TRUE|FALSE}";

-- leave most U*_D* and cclk pulled up initially, though we need to check whether config works with that. 
-- all other opaque ones as well...
-- D2,D3, pulled on board, PUDC pulled low on board
-- keep atca_ha pulled though they should be pulled on IPMC anyway


--ALIAS U123 IS U1_D(3 downto 2); --slicing doesn't work with attributes, leave all pulls on.
attribute FLOAT : string;
--attribute FLOAT of U1_CCLK : signal is "TRUE";
--attribute FLOAT of U2_CCLK : signal is "TRUE";
attribute FLOAT of U1_M,U1_PUDC_B : signal is "TRUE";
attribute FLOAT of U2_M,U2_PUDC_B : signal is "TRUE";

attribute PULLUP : string;
attribute PULLUP of U1_CPLD_SPARE : signal is "TRUE"; --have to pull all bits of vector to avoid syntax error
attribute PULLUP of U2_CPLD_SPARE : signal is "TRUE"; --have to pull all bits of vector to avoid syntax error


begin

--a<='Z';
--c<=a;




BOARD_CONF<=(others=>'Z');
CPLD1_CPLD2(11 downto 3)<=(others=>'Z');

CPLD1_CPLD2(0)<=U1_CPLD_SPARE(0)and U2_CPLD_SPARE(0);
CPLD1_CPLD2(1)<=U1_CPLD_SPARE(1);
CPLD1_CPLD2(2)<=U1_CPLD_SPARE(2);

--CPLD1_CPLD2<=(others=>'Z');
CPLDTOCTRLMEZZ<=(others=>'Z');
U1_CPLD_SPARE<=(others=>'Z');
U2_CPLD_SPARE<=(others=>'Z');
U1_M<=(others=>'Z');
U2_M<=(others=>'Z');
UZ_SPARE_SE<=(others=>'Z');
PUSH<=(others=>'Z');
ATCA_HA<=(others=>'Z');
IPMC_USER<=(others=>'Z');
IPMC_USER_3V3UP<=(others=>'Z');
ZONE1_HA<=(others=>'Z');
SPARE_CPLD1_3V3_UP<=(others=>'Z');
U1_D<=(others=>'Z');
U2_D<=(others=>'Z');
CLK1KHZ_CPLD1<='Z';
GCK_SINGLE_CPLD1<='Z';
IPMC_UART_RX<='Z';
IPMC_UART_TX<='Z';
MEZZ_UART_RX<='Z';
MEZZ_UART_TX<='Z';
U1_CCLK<='Z';
U1_CSI_ADV_B<='Z';
U1_DONE<='Z';
U1_DOUT_CSO_B<='Z';
U1_FCS2_B<='Z';
U1_INIT_B<='Z';
U1_PROGRAM_B<='Z';
U1_PUDC_B<='Z';
U1_RDWR_FCS<='Z';
U2_CCLK<='Z';
U2_CSI_ADV_B<='Z';
U2_DONE<='Z';
U2_DOUT_CSO_B<='Z';
U2_FCS2_B<='Z';
U2_INIT_B<='Z';
U2_PROGRAM_B<='Z';
U2_PUDC_B<='Z';
U2_RDWR_FCS<='Z';



end Behavioral;