started with cadence raw netlist. separated U1 and U2 to netlist-u1 and -u2 added PROCID pin which is tied to GND on U1, open on U2 identified special naming, identical for both processors: AC13 UNNAMED_1_RESPRT_I143_B : POR_override AD13 UNNAMED_1_BBRESPRT_I63_B :cclk_0 AY22 UNNAMED_1_BBRESPRT_I115_B : LED7/9 : --> LED_A BB21 UNNAMED_1_BBRESPRT_I119_B : LED8/10 : --> LED_B BD21 UNNAMED_1_RESPRT_I31_B : VRP/DCI bank65 H28 UNNAMED_8_RESPRT_I28_B : VRP bank71 -->u1.csv,u2.csv further processing for U1 only, so far. remove supply voltages, Vref (MGT) with help of excel --> u1-san1.csv sanitize further: cat u1-san1.csv |sed s.'4+4'.FF4. |sed s."U1_".. >u1-san2.csv result looks rather sane and compatible to VHDL/XDC naming comment out #: JTAG, XADC, T14 U1_INIT_B AB14 U1_M0 Y14 U1_M1 V14 U1_M2 AK14 U1_PROGRAM_B M14 U1_PUDC_B AM14 U1_RDWR_FCS to be done : add further comments in excel, swap columns and add columns for actual XDC syntax. further: probably best to be done with tr/sed/awk etc: turn buses to XDC compatible index notation some remarks: MGT clocls are not indexed consecutively, but since they carry all the same signal, we can just as well renumber them as we wish. no need to relate to the PCB indexing at a later stage, I would think. how would we like to name differential buses ? name__[index] ? Any other preference, eg. just a simple bus with even/odd assigned to p/n ? all bus renaming has been done in1-san3.csv, except MGT5_clk cat netlist-u2.txt |sed s._U2._U1. |sed s.U2_.U1_. |diff netlist-u1.txt - |less tells us that both FPGAs have the same pin constraints with exception of the MGT_CLK indices which we wanted to sanitize anyway, since here the reference to the board level index doesn't make sense: the signals are all the same anyway. final command for translating .csv to something sensible: cat u1-san3.csv |tr [ $ |sed s.";$;".$. |tr $ [|tr ] $ |sed s.";$;".$. |tr $ ] |tr -s ";"|tr ";" " " >u1-san3.txt